Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor structure including methods (128) for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The methods comprise etching (140, 200) portions of an upper electrode, etching (141, 201) ferroelectric material, and etching (142, 202) a lower electrode to define a patterned ferroelectric capacitor structure, and etching (143, 206) a portion of a lower electrode diffusion barrier structure. The methods further comprise ashing (144, 203) the patterned ferroelectric capacitor structure using a first ashing process, performing (145, 204) a wet clean process after the first ashing process, and ashing (146, 205) the patterned ferroelectric capacitor structure using a second ashing process directly after the wet clean process at a high temperature in an oxidizing ambient.

Abstract: The present invention facilitates data retention lifetimes for ferroelectric devices by improving switched polarization of ferroelectric memory cells. A ferroelectric memory device comprising ferroelectric memory cells is provided (702). A duration for applying a DC bias to the ferroelectric memory cells is selected (704) according to at least a desired switched polarization improvement. A magnitude for applying the DC bias to the ferroelectric memory cells is also selected (706) according to at least the desired switched polarization improvement. Further, an elevated temperature is selected for applying the DC bias to the ferroelectric memory cells is also selected (708) according to at least the desired switched polarization improvement. Subsequently, the DC bias is applied to the ferroelectric memory cells (710), which activates one or more inactive domains within the ferroelectric memory cells and increases initial polarization values.

Abstract: Methods (100) are provided for fabricating a ferroelectric capacitor in a semiconductor device wafer, comprising forming (118) a lower electrode, depositing (126) PZT ferroelectric material on the lower electrode at a temperature below 450 degrees C., and forming (128) an upper electrode on the PZT. Methods are also provided for fabricating a ferroelectric memory cell in a semiconductor device wafer, comprising forming (106) a transistor in the wafer, forming (108) a nickel silicide structure on the gate or a source/drain of the transistor, forming (110) a dielectric over the transistor, forming (112) a conductive contact extending through the dielectric to the silicide structure, forming (114, 116, 118, 120) a lower electrode on at least a portion of the conductive contact, forming (126) PZT ferroelectric material above and in contact with the lower electrode at a temperature below 450 degrees C.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract: Semiconductor devices and fabrication methods are disclosed, in which one or more low silicon-hydrogen SiN barriers are provided to inhibit hydrogen diffusion into ferroelectric capacitors and into transistor gate dielectric interface areas. The barriers may be used as etch stop layers in various levels of the semiconductor device structure above and/or below the level at which the ferroelectric capacitors are formed so as to reduce the hydrogen related degradation of the switched polarization properties of the ferroelectric capacitors and to reduce negative bias temperature instability in the device transistors.

Abstract: Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.