Patents by Inventor K. Y. Ramanujam

K. Y. Ramanujam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8622021
    Abstract: A method of increasing mean time between cleans of a plasma etch chamber and chamber parts lifetimes is provided. Semiconductor substrates are plasma etched in the chamber while using at least one sintered silicon nitride component exposed to ion bombardment and/or ionized halogen gas. The sintered silicon nitride component includes high purity silicon nitride and a sintering aid consisting of silicon dioxide. A plasma processing chamber is provided including the sintered silicon nitride component. A method of reducing metallic contamination on the surface of a silicon substrate during plasma processing is provided with a plasma processing apparatus including one or more sintered silicon nitride components. A method of manufacturing a component exposed to ion bombardment and/or plasma erosion in a plasma etch chamber, comprising shaping a powder composition consisting of high purity silicon nitride and silicon dioxide and densifying the shaped component.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: January 7, 2014
    Assignees: Lam Research Corporation, Ceradyne Inc.
    Inventors: Travis R. Taylor, Mukund Srinivasan, Bobby Kadkhodayan, K. Y. Ramanujam, Biljana Mikijelj, Shanghua Wu
  • Publication number: 20110021031
    Abstract: A method of increasing mean time between cleans of a plasma etch chamber and chamber parts lifetimes is provided. Semiconductor substrates are plasma etched in the chamber while using at least one sintered silicon nitride component exposed to ion bombardment and/or ionized halogen gas. The sintered silicon nitride component includes high purity silicon nitride and a sintering aid consisting of silicon dioxide. A plasma processing chamber is provided including the sintered silicon nitride component. A method of reducing metallic contamination on the surface of a silicon substrate during plasma processing is provided with a plasma processing apparatus including one or more sintered silicon nitride components. A method of manufacturing a component exposed to ion bombardment and/or plasma erosion in a plasma etch chamber, comprising shaping a powder composition consisting of high purity silicon nitride and silicon dioxide and densifying the shaped component.
    Type: Application
    Filed: October 27, 2008
    Publication date: January 27, 2011
    Inventors: Travis R. Taylor, Mukund Srinivasan, Bobby Kadkhodayan, K.Y. Ramanujam, Biljana Mikijelj, Shanghua Wu
  • Patent number: 7040952
    Abstract: A method for preventing de-lamination of semiconductor wafer film stacks during a linear belt-type chemical mechanical planarization (CMP) process is provided. The method implements a pulsed polishing head rotation during a CMP process to maintain a slurry distribution across the width of a belt pad. The slurry distribution is maintained in a manner that prevents de-lamination of a wafer film having weak adhesion characteristics. Thus, the pulsed polishing head rotation implemented by the method reduces de-lamination of low-K material film layers during the CMP process.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: May 9, 2006
    Assignee: Lam Research Corporation
    Inventors: Sridharan Srivatsan, Ramesh Gopalan, K. Y. Ramanujam
  • Publication number: 20030060145
    Abstract: A multi-step polishing system, and a process for polishing a workpiece using the system. The system includes one or more polishing stations. The workpiece is polished in the presence of an oxidizer-free medium, and subsequently, the workpiece is polished in the presence of an oxidizing medium. This polishing sequence extends the life of the polishing pads and provides for a more uniform polish.
    Type: Application
    Filed: August 23, 2001
    Publication date: March 27, 2003
    Inventors: Youlin J. Li, Stephen Jew, Sridharan Srivatsan, K.Y. Ramanujam
  • Publication number: 20020185467
    Abstract: An interlocking polishing belt apparatus is disclosed. The interlocking polishing belt apparatus includes an interlocking belt, which includes a plurality of studs each having an upper stud end and a lower stud end. In addition, the interlocking polishing belt apparatus includes a polishing belt that is in contact with the interlocking belt. The polishing belt has a plurality of polishing belt stud holes, each configured to interlock with an upper stud end.
    Type: Application
    Filed: July 23, 2002
    Publication date: December 12, 2002
    Applicant: Lam Research Corporation
    Inventors: John Boyd, K. Y. Ramanujam, Sridharan Srivatsan, Xuyen Pham
  • Patent number: 5714037
    Abstract: Methods for improving adhesion between various materials utilized in the fabrication of integrated circuits. A first method relates to improving adhesion between a silicon nitride layer and a silicon dioxide layer. The method includes treating a surface of the silicon dioxide layer with a nitrogen plasma in a reactive ion etching process prior to depositing the silicon nitride film on the surface of the silicon dioxide layer. A second method relates to improving adhesion between a silicon nitride layer and a polyimide layer. The method includes the step of treating a surface of the silicon nitride layer with a oxygen/argon plasma in a reactive ion etching process prior to depositing the polyimide layer film on the surface of the silicon nitride layer. A third method relates to improving adhesion between a photoresist layer and a metal.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: February 3, 1998
    Assignee: Microunity Systems Engineering, Inc.
    Inventors: Kumar D. Puntambekar, K. Y. Ramanujam, Tom Blount, Ray Liang