Patents by Inventor Ka Heng The

Ka Heng The has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6465890
    Abstract: Integrated circuit packages having offset segmentation, or splitting, of package power and/or ground layers and methods for preventing delamination in package substrates having segmented power and/or ground layers are described. The package substrate includes a plurality of split power and/or ground plane layers that are isolated by split lines. The split lines from at least two of the split power and/or ground plane layers are offset relative to one another. In some embodiments, in addition to being offset, the split lines may be arranged to minimize their respective cross-over points, as well as convoluted to increase their effective length.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 15, 2002
    Assignee: National Semiconductor Corporation
    Inventors: Anindya Poddar, Ka Heng The
  • Patent number: 5789806
    Abstract: A leadframe including bendable support arms for downsetting a die attach pad and method are disclosed herein. The leadframe includes at least one frame member and the die attach pad. At least two distinct, readily bendable support arms are connected with and extend between the die attach pad and the frame member. The support arms are configured to be bent in a predetermined way in the method of the invention such that when they are bent they provide previously unattainable amounts of die attach pad downset within the overall configuration of the leadframe.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: August 4, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Charlie Kho Chua, Ka-Heng The, Peter Howard Spalding
  • Patent number: 5057907
    Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: October 15, 1991
    Assignee: National Semiconductor Corp.
    Inventors: Boon K. Ooi, Shiann-Ming Liou, Ka-Heng The, Norman L. Gould