Abstract: Apparatus and methods are provided for TxRU carrier switch. In one embodiment, the UE is configured with an anchor carrier in an anchor cell and one or more secondary carriers. In one embodiment, the TxRU carrier switch is configured as supplementary uplink (SUL)-based carrier switch with supplementary carriers or configured as a CA-based carrier switch with supplementary cells. In one embodiment, the one or more secondary carriers are supplementary carriers of the anchor cell, and wherein the anchor carrier is TDD carrier or frequency division duplex (FDD) carrier, and wherein the supplementary carrier is configured as a TDD carrier, a FDD carrier, a supplementary uplink carrier (SUL), or a supplementary downlink carrier (SDL). In another embodiment, the one or more secondary carriers are supplementary cells different from the anchor cell, and wherein the supplementary cells are configured with MAC control element (CE).

Abstract: A multi-channel payment method for a multi-channel payment system comprises the payer or the payee who initiated the payment request logs in to the multi-channel payment system; the payer or the payee who initiated the payment request placing an order in the multi-channel payment system, wherein the order comprises a designated payment gateway; the multi-channel payment system determining a predicted fee of the order according to the designated payment gateway, past order records, and a real-time exchange rate; the multi-channel payment system performing an anti-money laundering verification of the order; the payer reviewing the order and the predicted fee through a multiple auditing method; and the multi-channel payment system executing payment from the payer to the payee according to the order and the designated payment gateway, and storing a payment detail of the order.

Abstract: A display device includes a first substrate, a light-emitting element, a light conversion layer, and a color filter layer. The light-emitting element is disposed on the first substrate. The light conversion layer is disposed on the light-emitting element. In addition, the color filter layer is overlapped the light-emitting element and the light conversion layer.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A backlight control circuit for a surface light emitting device is provided. The backlight control circuit includes a driving circuit. The driving circuit is configured to generate a plurality of driving currents to drive the surface light emitting device such that a plurality of backlight blocks of the surface light emitting device generate a plurality of brightness values. The surface light emitting device is divided into a first backlight area and a second backlight area. The second backlight area is closer to an edge of the surface light emitting device than the first backlight area. A first driving current of the plurality of driving currents is utilized for driving the light source of the first backlight area. A second driving current of the plurality of driving currents is utilized for driving the light source of the second backlight area. The second driving current is greater than the first driving current.

Abstract: Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process: 0 ? ? ? T ? ? 1 T ? ? 2 ? A ? ( T ) ? dT - ? T ? ? 1 T ? ? 3 ? E ? ( T ) ? dT ? ? < 0.01 wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.

Abstract: The present disclosure provides a test system and method. The test system is configured to analyze a system platform and includes a data collector and a test monitor. The data collector is configured to receive a signal transmitted between a controller and a memory of the system platform and is configured to process the signal to generate a processed signal. The test monitor is configured to encode the processed signal into a log information, so as to determine an operation status of the system platform according to the log information.

Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.

Abstract: An object detection method is suitable for a virtual reality system. The object detection method includes a plurality of first cameras of a head-mounted display (HMD) to capture a plurality of first frames. A plurality of second frames are captured through a plurality of second cameras in a tracker, wherein, the object detector searches for the object position in the first frames and the second frames.

Abstract: A fault analysis device and a fault analysis method of the fault analysis device are provided. A sensing circuit senses a first distorted signal on a first signal transmission path of an abnormal signal device when the abnormal signal device performs a preset operation. A signal generating circuit provides a fault test signal to a second signal transmission path of a standard device corresponding to the first signal transmission path when the standard device performs the preset operation, so as to generate a second distorted signal on the second signal transmission path, where the first distorted signal and the second distorted signal have the same signal distortion characteristics.

Abstract: An integrated motor and drive assembly is disclosed and includes a housing, a motor and a drive. The housing includes a motor-accommodation portion and a drive-accommodation portion. The drive includes a power board and a control board. The power board is made of a high thermal conductivity substrate and includes a power element and an encoder disposed on the first side, the first side faces the motor, the power board and the motor are stacked along a first direction, and the second side contacts the housing to from a heat-dissipating route. The control board is disposed adjacent to the power board. The control board and the power board are arranged along a second direction perpendicular to the first direction, and the first direction is parallel to an axial direction of the motor. A part of the power board and a part of the control board are directly contacted to form an electrical connection.

Abstract: A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.

Abstract: A preparation method of a lithium iron phosphate cathode material includes steps of (a) providing a phosphoric acid, an iron powder, a carbon source, wherein the phosphoric acid and the iron powder are reacted to produce a first product, and the first product is amorphous iron phosphate with chemical formula of a-FePO4·xH2O (x>0); (b) providing a lithium salt mixture, wherein the lithium salt mixture includes a lithium hydroxide and a lithium carbonate; (c) grinding and mixing the first product, the carbon source, and the lithium salt mixture; (d) calcining the first product and the lithium salt mixture to produce a precursor, wherein the precursor has a formula of Fe3(PO4)2·8H2O+Li3PO4; and (e) calcining the precursor and the carbon source to obtain the lithium iron phosphate cathode material.

Abstract: A gene editing system comprising: (a) a Type V CRISPR nuclease polypeptide or a first nucleic acid encoding the Type V CRISPR nuclease polypeptide; (b) a reverse transcriptase (RT) polypeptide or a second nucleic acid encoding the RT polypeptide; (c) a guide RNA (gRNA) or a third nucleic acid encoding the gRNA, wherein the gRNA comprises one or more binding sites recognizable by the Type V CRISPR nuclease (CRISPR nuclease binding sites) and a spacer sequence specific to a target sequence within a genomic site of interest, the target sequence being adjacent to a protospacer adjacent motif (PAM); and (d) a reverse transcription donor RNA (RT donor RNA) or a fourth nucleic acid encoding the RT donor RNA, wherein the RT donor RNA comprises a primer binding site (PBS) and a template sequence.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: Various solutions for providing a unified control channel framework in mobile communications are described. An apparatus receives a first-stage downlink control information (DCI) from a network node. The first-stage DCI indicates first scheduling information associated with a second-stage DCI. Then, the apparatus receives the second-stage DCI from the network node according to the first scheduling information. The second-stage DCI indicates second scheduling information associated with one or more carriers or cells or indicates non-scheduling information associated with one or more features. Also, the apparatus performs operations including either one of the following: (1) performing a PDSCH reception or a PUSCH transmission on at least one of the one or more carriers or cells according to the second scheduling information; and (2) applying the non-scheduling information in an event that the apparatus supports at least one of the one or more features.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Abstract: A fan module comprises a frame, a wire-stopping structure, an impeller and a circuit board. The frame includes a frame wall, a base, a plurality of static blades and a connector. A wire groove formed on an outside of the frame wall to accommodate a wire. The static blades are radially connected to the base and the frame wall. The connector is formed on the outside of the frame wall and extended from one end of the wire groove to the base along one of the static blades. The connector includes a plurality of pins. The wire-stopping board is fixed to the frame wall to cover the wire groove. The impeller is disposed in the frame. The circuit board is disposed in the frame and located on the base. The circuit board includes a plurality of pin holes, and the pin holes are electrically connected to the pins.

Abstract: Analog-to-digital converter circuitry includes comparator circuitry, capacitor analog-to-digital converter circuitry (CDA), and successive approximation register (SAR) circuitry. The comparator circuitry includes a non-inverting input and an inverting input to selectively receive a differential voltage signal, and an output. The CDAC circuitry includes a first capacitor network having a first plurality of capacitors. A first capacitor of the first plurality of capacitors includes a first terminal connected to the non-inverting input and a second terminal selectively connected to a first voltage potential and a second voltage potential. The first voltage potential is greater than the second voltage potential. The SAR circuitry is connected to the output and the first capacitor network, and connects, during a first period, the second terminal of the first capacitor to the second voltage potential.

Abstract: A digital-to-analog converter (DAC)-based voltage-mode transmit driver architecture. One example transmit driver circuit generally includes an impedance control circuit coupled to a plurality of DAC driver slices. The impedance control circuit generally includes a tunable impedance configured to be adjusted to match a load impedance for the transmit driver circuit. Another example transmit driver circuit generally has an output impedance that is smaller than the load impedance for the transmit driver circuit, such that an output voltage swing at differential output nodes of the transmit driver circuit is greater than a voltage of a power supply rail. Another example transmit driver circuit generally includes a predriver circuit with a first inverter coupled to a first output of the predriver circuit and a second inverter coupled to a second output of the predriver circuit, the transistors in at least one of the first inverter or the second inverter having different strengths.