Abstract: An apparatus (e.g., an access point (AP) or a non-AP station (STA)) detects a non-primary subband of an operating bandwidth comprising a primary subband and the non-primary subband to be idle. The apparatus controls a transmit power in performing transmission on at least the non-primary subband.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.

Abstract: Various techniques and schemes pertaining to extremely-high throughput (EHT) multi-link maximum channel switching in wireless communications are described. A station (STA) multi-link device (MLD) receives an indication from a reporting access point (AP) affiliated with an AP MLD on one link of multiple links. The STA MLD determines a channel switching time when a reported AP switches from operating in a current channel of the reported AP to operating in a new channel on one other link of the multiple links based on the indication.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure includes a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.

Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.

Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.

Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.

Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip interposed between a lower transparent substrate and an upper transparent substrate. The device chip comprises a semiconductor substrate comprising a device region surrounded by a pad region, in which the pad region comprises a plurality of notches along the edges of the semiconductor substrate. A dielectric layer is between the semiconductor substrate and the upper transparent substrate, comprising a plurality of pads formed therein and substantially aligned with the plurality of notches, respectively. A plurality of metal lines is disposed under a bottom surface of the lower transparent substrate. A plurality of solder balls disposed under the plurality of metal lines, respectively.

Abstract: A package structure for an optoelectronic device. The package structure comprises a device chip reversely disposed on a first substrate, which comprises a second substrate and a first dielectric layer between the first and second substrates. The first dielectric layer comprises a pad formed in a corner of the first dielectric layer non-overlapping the second substrate, such that the surface and sidewall of the pad are exposed. A metal layer is formed directly on the exposed surface of the pad and covers the second substrate. A protective layer covers the metal layer, having an opening to expose a portion of the metal layer on the second substrate. A solder ball is disposed in the opening, electrically connecting to the metal layer. The invention also discloses a method for fabricating the same.

Abstract: A bonding pad structure for an optoelectronic device. The bonding pad structure comprises a carrier substrate having a bonding pad region and an optoelectronic device region. An insulating layer is disposed on the carrier substrate, having an opening corresponding to the bonding pad region. A bonding pad is embedded in the insulating layer under the opening to expose the top surface thereof. A device substrate is disposed on the insulating layer corresponding to the optoelectronic device region. A cap layer covers the device substrate and the insulating layer excluding the opening. A conductive buffer layer is disposed in the opening to directly contact the bonding pad. The invention also discloses a method for fabricating the same.

Abstract: Isolation structure for CMOS image sensor device chip scale packages and fabrication methods thereof. A CMOS image sensor chip scale package includes a transparent substrate configured as a support structure for the package. The transparent substrate includes a first cutting edge and a second cutting edge. A CMOS image sensor die with a die circuitry is mounted on the transparent substrate. An encapsulant is disposed on the substrate encapsulating the CMOS image sensor die. A connection extends from the die circuitry to a plurality of terminal contacts for the package on the encapsulant, wherein the connection is exposed by the first cutting edge. An isolation structure is disposed on the first cutting edge passivating the exposed connection and co-planed with the second cutting edge.