Patents by Inventor Kai-Chun Chen

Kai-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990100
    Abstract: An e-paper identification card system including an e-paper identification card and a data updating apparatus is provided. The e-paper identification card is configured to display first image information. The data updating apparatus is electrically connected to the e-paper identification card. The data updating apparatus is configured to update the e-paper identification card according to the first image information to drive the e-paper identification card to display second image information. In addition, an e-paper identification card is also provided.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: May 21, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chih-Chun Chen, Huei-Chuan Lee, Cheng-Hsien Lin, Shuo-En Lee, Kai-Yi Cho
  • Patent number: 11978720
    Abstract: A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai Jun Zhan, Chin-Fu Kao, Kuang-Chun Lee, Ming-Da Cheng, Chen-Shien Chen
  • Patent number: 11973021
    Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: April 30, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Kai-Chun Chen, Shih-Ming Tseng, Hsing-Chao Liu, Hsiao-Ying Yang
  • Publication number: 20240115616
    Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 11, 2024
    Inventors: Po-Cheng Lin, Pi-Chun Huang, Zih-Han Hong, Ming-Hsi Chuang, Yi-Chun Lin, Chia-Hsin Lee, Chun-Hung Chen, Chao-Liang Chang, Kai-Ling Zhang
  • Patent number: 11955484
    Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second S/Ds. The first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. A width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. A width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. The insulators are disposed on the semiconductor substrate. The first and second semiconductor fins are sandwiched by the insulators. The gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. The first and second S/Ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Jung Chen, I-Chih Chen, Chih-Mu Huang, Kai-Di Wu, Ming-Feng Lee, Ting-Chun Kuan
  • Publication number: 20230105036
    Abstract: A semiconductor device includes a first metal layer, a second metal layer, and an inter-metal dielectric layer disposed between the first metal layer and the second metal layer. The inter-metal dielectric layer includes: a first dielectric layer disposed on the first metal layer and in direct contact with the first metal layer, wherein the first dielectric layer has a stress value less than 0; a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer has a stress value greater than 0; and a third dielectric layer disposed on the second dielectric layer, wherein the third dielectric layer has a stress value less than 0. A thickness of the third dielectric layer is greater than a thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.
    Type: Application
    Filed: September 17, 2021
    Publication date: April 6, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Kai-Chun CHEN, Shih-Ming TSENG, Hsing-Chao LIU, Hsiao-Ying YANG
  • Publication number: 20210267546
    Abstract: Besides of a forehead thermometer and a thermography imaging equipment, other temperature measuring tools requires a direct contact with the human bodies, however, the forehead thermometer used for measuring is in a close distance, this time consuming and an additional risk of getting infected will happen; the thermography imaging equipment has an advantage of rapidly measuring, but the cost thereof is high and could not be prevailed; as such, the present invention is to consider a product combining a temperature measuring tool and a wearable headset, and a wired or a wireless means is used for transmitting data with a smart phone, a virtual button of an APP or a button module of the headset can switch functions, the relevant data is displayed on a screen of the smart phone, moreover, the measured temperature is uploaded to a cloud for allowing a quarantine inspector to perform an initial termination.
    Type: Application
    Filed: September 18, 2020
    Publication date: September 2, 2021
    Inventor: Kai-Chun CHEN
  • Publication number: 20210251331
    Abstract: The present invention is to continue the concept of a replaceable upper of offloading shoe, and further improve the processing capability. Thus this present invention is to reform the outsole separation structure of a replaceable upper of shoe.
    Type: Application
    Filed: September 18, 2020
    Publication date: August 19, 2021
    Inventor: Kai-Chun CHEN
  • Publication number: 20060129862
    Abstract: The computer comprises a power supply for supplying power. The power saving device for network controller of computer comprises a network controller, a switch connecting between the power supply and the network controller, a control circuit connecting the power supply and the switch and a network connector. The network comprises a network pin and a power saving pin. The network pin is electrically connected the network controller. The power saving pin is electrically connected the control circuit. When access to the Internet is not required, the computer cuts off power to the network controller via the power saving pin to reduce power consumption.
    Type: Application
    Filed: March 28, 2005
    Publication date: June 15, 2006
    Inventors: Chun-Hu Liu, Kai-Chun Chen
  • Patent number: D1027976
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 21, 2024
    Assignee: VIVOTEK INC.
    Inventors: Kuan-Hung Chen, Kai-Sheng Chuang, Chia-Chi Chang, Yu-Fang Huang, Kai-Ting Yu, Wen-Chun Chen, Shu-Jung Hsu, Tsao-Wei Hung