Patents by Inventor Kai Frohberg

Kai Frohberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance
    Publication number: 20120153405
    Abstract: In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished.
    Type: Application
    Filed: August 2, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jens Heinrich, Kai Frohberg, Torsten Huisinga, Ronny Pfuetzner
  • Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer
    Patent number: 8198147
    Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: June 12, 2012
    Assignee: GlobalFoundries, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Method of Forming Metal Silicide Regions
    Publication number: 20120115326
    Abstract: The method described herein involves the formation of metal silicide regions. The method may involve forming a layer of refractory metal on a structure comprising silicon, forming a layer of silicon on the layer of refractory metal and, after forming the layer of silicon, performing at least one heat treatment process to form a metal silicide region in the structure.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai Frohberg, Jens Heinrich, Katrin Reiche
  • Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach
    Publication number: 20120091535
    Abstract: By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.
    Type: Application
    Filed: December 27, 2011
    Publication date: April 19, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai FROHBERG, Frank FEUSTEL, Thomas WERNER, Uwe GRIEBENOW
  • Void sealing in a dielectric material of a contact level of a semiconductor device comprising closely spaced transistors
    Patent number: 8129276
    Abstract: In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: March 6, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Ralf Richter, Kai Frohberg, Holger Schuehrer
  • Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region
    Patent number: 8110487
    Abstract: By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 7, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Kai Frohberg, Christoph Schwan, Kerstin Ruttloff
  • Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric
    Publication number: 20120025318
    Abstract: Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.
    Type: Application
    Filed: June 7, 2011
    Publication date: February 2, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Peter Javorka, Kai Frohberg
  • Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach
    Patent number: 8105962
    Abstract: By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: January 31, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Frank Feustel, Thomas Werner, Uwe Griebenow
  • SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE
    Publication number: 20120021581
    Abstract: By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 26, 2012
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches
    Patent number: 8101524
    Abstract: During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: January 24, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kai Frohberg, Matthias Schaller, Massud Aminpur
  • Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric
    Publication number: 20120001263
    Abstract: In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the basis of a substantially uniform interlayer dielectric material, for instance in the form of a silicon nitride material, which may have a similar removal rate compared to the dielectric cap material, the spacer elements and the like of the gate electrode structures. Consequently, a pronounced degree of recessing of the interlayer dielectric material may be avoided, thereby reducing the risk of forming metal residues upon removing any excess material of the gate metal.
    Type: Application
    Filed: December 16, 2010
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Kai Frohberg
  • Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction
    Publication number: 20120001323
    Abstract: In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses.
    Type: Application
    Filed: December 13, 2010
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Torsten Huisinga, Jens Heinrich, Kai Frohberg, Frank Feustel
  • Selective Shrinkage of Contact Elements in a Semiconductor Device
    Publication number: 20110291292
    Abstract: In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.
    Type: Application
    Filed: May 6, 2011
    Publication date: December 1, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai Frohberg, Ralf Richter, Torsten Huisinga, Katrin Reiche
  • Semiconductor Device Comprising Contact Elements and Metal Silicide Regions Formed in a Common Process Sequence
    Publication number: 20110266638
    Abstract: A metal silicide in sophisticated semiconductor devices may be provided in a late manufacturing stage on the basis of contact openings, wherein the deposition of the contact material, such as tungsten, may be efficiently combined with the silicidation process. In this case, the thermally activated deposition process may initiate the formation of a metal silicide in highly doped semiconductor regions.
    Type: Application
    Filed: December 9, 2010
    Publication date: November 3, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Kai Frohberg, Rainer Giedigkeit, Robert Binder, Stephan Waidmann
  • Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor
    Patent number: 8048736
    Abstract: By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • SOI semiconductor device with reduced topography above a substrate window area
    Patent number: 8048726
    Abstract: In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Kai Frohberg, Sven Mueller, Kerstin Ruttloff
  • Method and test structure for estimating focus settings in a lithography process based on CD measurements
    Patent number: 8040497
    Abstract: By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime
    Publication number: 20110241167
    Abstract: Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode.
    Type: Application
    Filed: November 9, 2010
    Publication date: October 6, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Frank Feustel, Thomas Werner, Kai Frohberg
  • Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer
    Patent number: 8030209
    Abstract: During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDDRIES Inc.
    Inventors: Thomas Werner, Kai Frohberg, Frank Feustel
  • THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION
    Publication number: 20110223732
    Abstract: Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.
    Type: Application
    Filed: May 10, 2011
    Publication date: September 15, 2011
    Inventors: Uwe Griebenow, Jan Hoentschel, Kai Frohberg, Heike Berthold, Katrin Reiche, Frank Feustel, Kerstin Ruttloff