Abstract: A display device and a display are provided. The display device includes: a drive substrate including a drive circuit, a light-emitting device array, a micro-optical structure, and a color conversion layer array. The light-emitting device array is disposed on a surface of the drive substrate and includes multiple light-emitting devices electrically connected to the drive circuit, and light emitted by the multiple light-emitting devices is light with a same color. The micro-optical structure is disposed above the light-emitting device array and used to refract the light emitted by the light-emitting device array to a uniform refraction angle. The color conversion layer array is disposed above the micro-optical structure, the multiple light-emitting devices respectively correspond to multiple color conversion layers in the color conversion layer array, and the color conversion layer array is used to convert the light emitted by the multiple light-emitting devices into light with a required color.

Abstract: A single wafer spin cleaning apparatus with soaking, cleaning, and etching functions in accordance with the present invention includes a spin driver device, a wafer spin chuck, and a wafer support disk. The wafer spin chuck is driven by the spin driver device to spin. The wafer support disk is annular and surrounds the wafer spin chuck, can act relative to the wafer spin chuck to a wafer support position or a wafer disengagement position, and includes a soaking trough. The wafer support disk at the wafer support position can support a wafer such that the wafer is soaked in processing liquid injected in the soaking trough for implementing a high efficient cleaning or etching process.

Abstract: An information handling system includes a printed circuit board, a screw, and a processor. The printed circuit board includes a through hole via. The through hole via includes top and bottom sections plated with a conductive plating material, and a middle section without any conductive plating material. The screw in physical communication with the top, middle, and bottom sections of the through hole via in the printed circuit board. The processor determines whether an electrical circuit is formed between the screw, the top section of the through hole via, and the bottom section of the through hole via. Based on the determination of the electrical circuit being formed, the processor provides an indication that no intrusion has been made into the information handling system.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Abstract: A micro-LED chip includes an epitaxial structure, which includes first and second doped type semiconductor layers and an active layer disposed between the first and second doped type semiconductor layers; a light-emitting side of the first doped type semiconductor layer facing away from the active layer is provided with a patterned structure; and an elongated edge a of the micro-LED chip, a thickness b of the micro-LED chip, and a peak-valley height difference c of the patterned structure satisfy: 0.01?b/a?6, and 0.01?c/b?0.3. By designing a structure size and/or a shape of the micro-LED chip combined with designing the peak-valley height difference of the patterned structure to satisfy the condition of 0.01?c/b?0.3, power of laser lift-off operation can be reduced and a process window thereof is enlarged, and light extraction efficiency of the micro-LED chip is achieved. And a display device using the micro-LED chip is provided.

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.

Abstract: An active noise control (ANC) circuit is used for generating an anti-noise signal, and has a plurality of filters including at least one first filter and at least one second filter. The at least one first filter generates at least one first filter output, wherein each of the at least one first filter has at least one non-static filter and at least one static filter connected in a series fashion. The at least one second filter generates at least one second filter output, wherein each of the at least one second filter has at least one adaptive filter. The anti-noise signal is jointly controlled by the at least one first filter output and the at least one second filter output. The at least one first filter and the at least one second filter are connected in a parallel fashion.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.

Abstract: An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: An open-loop inductor current emulating circuit is provided. A current sensor circuit senses a current flowing through a first terminal of a low-side switch to output a current sensed signal. An emulation controller circuit outputs a plurality of charging current signals according to currents of a plurality of rising waveforms of the current sensed signal. The emulation controller circuit outputs a plurality of discharging current signals according to currents of a plurality of falling waveforms of the current sensed signal. A charging and discharging circuit generates a plurality of charging currents according to the charging current signals, and generates a plurality of discharging currents according to the discharging current signals. The charging and discharging circuit alternatively outputs the charging currents and the discharging currents to the capacitor to charge and discharge the capacitor multiple times, thereby achieving a purpose of emulating an inductor current.

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: The display system comprising a main control module and a display module is provided. The main control module comprises a display driving circuit and a timing control circuit. The display driving circuit is used to output a display driving signal. The timing control circuit is coupled to the display driving circuit to receive the display driving signal, and convert the display driving signal into a digital signal. The display module comprises a first display panel to an N-th display panel, coupled to the timing control circuit and receiving the digital signal, so as to display corresponding multimedia content according to the digital signal, wherein N is a positive integer greater than 1, and the main control module is independently coupled to the display module.

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.