Abstract: A system and method are disclosed for processing semiconductors. An embodiment comprises a reaction chamber for processing wafers and having walls tapering at an angle that is greater than 0 degrees and less than about 35 degrees from a first end optionally having a diameter of 341 to 380 millimeters to a second end optionally having a diameter of 300 to 340 millimeters at a second end, with gas flow from the first end to the second end, and having at least one deposition injector near the first end of the reaction chamber and having a plurality of injector openings that disperse injection material across a cross section of the reaction chamber for forming a deposition layer.

Abstract: A pixel circuit structure applied in an LCD panel, which has a common voltage and includes at least one data line, is provided. The pixel circuit structure includes a first and a second circuit. The first circuit includes a first switch and a first capacitor. The second circuit includes a second switch, a third switch and a second capacitor. One end of the first capacitor receives the common voltage. Two ends of the first switch are respectively coupled to the data line and the other end of the first capacitor. The second and the third switch are coupled serially between the data line and a voltage source. One end of the second capacitor receives the common voltage, and the other end is coupled between the second and the third switch. The potential difference between the two ends of the first capacitor is different from that of the second capacitor.

Abstract: A pixel circuit structure applied in an LCD panel, which has a common voltage and includes at least one data line, is provided. The pixel circuit structure includes a first and a second circuit. The first circuit includes a first switch and a first capacitor. The second circuit includes a second switch, a third switch and a second capacitor. One end of the first capacitor receives the common voltage. Two ends of the first switch are respectively coupled to the data line and the other end of the first capacitor. The second and the third switch are coupled serially between the data line and a voltage source. One end of the second capacitor receives the common voltage, and the other end is coupled between the second and the third switch. The potential difference between the two ends of the first capacitor is different from that of the second capacitor.