Patents by Inventor Kai-Lung Cheng
Kai-Lung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996630Abstract: An antenna structure includes a ground element, a first radiation element, a second radiation element, a third radiation element, and a nonconductive support element. The first radiation element is coupled to a first grounding point on the ground element. The second radiation element has a feeding point. The second radiation element is adjacent to the first radiation element. The third radiation element is coupled to a second grounding point on the ground element. The third radiation element is adjacent to the second radiation element. The first radiation element, the second radiation element, and the third radiation element are disposed on the nonconductive support element. The second radiation element is at least partially surrounded by the first radiation element. The third radiation element is at least partially surrounded by the second radiation element.Type: GrantFiled: September 2, 2022Date of Patent: May 28, 2024Assignee: QUANTA COMPUTER INC.Inventors: Yu-Chen Zhao, Chung-Ting Hung, Chin-Lung Tsai, Ying-Cong Deng, Kuan-Hsien Lee, Yi-Chih Lo, Kai-Hsiang Chang, Chun-I Cheng, Yan-Cheng Huang
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Patent number: 11996633Abstract: A wearable device includes a ground element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, and a fifth radiation element. The first radiation element has a feeding point, and is coupled to a first grounding point on the ground element. A slot region is surrounded by the first radiation element and the ground element. The second radiation element is coupled to a second grounding point on the ground element. The third radiation element is coupled to the second grounding point. The third radiation element and the second radiation element substantially extend in opposite directions. The fourth radiation element and the fifth radiation element are disposed inside the slot region. An antenna structure is formed by the first radiation element, the second radiation element, the third radiation element, the fourth radiation element, and the fifth radiation element.Type: GrantFiled: September 6, 2022Date of Patent: May 28, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chun-I Cheng, Chung-Ting Hung, Chin-Lung Tsai, Kuan-Hsien Lee, Yu-Chen Zhao, Kai-Hsiang Chang
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Patent number: 11630720Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: GrantFiled: June 24, 2021Date of Patent: April 18, 2023Assignee: Western Digital Technologies, Inc.Inventors: Parvaneh Alavi, Kai-Lung Cheng, Yun-Tzuo Lai, Haining Liu
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Publication number: 20230083151Abstract: Disclosed are a brewing module and its brewing method. The brewing module is combined with a smart brewing machine for use and includes a brewing control module with an inductive identification unit, and a brewing material package unit with a package and an identification member, and the package contains a brewing material, and the identification member is installed onto the package. The inductive identification unit is used for sensing, recognizing and reading the identification member, and the identification member contains information of the brewing material and information and brewing execution information of the brewing material. In this way, the source of brewing material required for the production of a brewed beverage can be ensured, and errors easily caused by human operations can be avoided, so that the quality of the brewed beverage can be consistent.Type: ApplicationFiled: December 22, 2021Publication date: March 16, 2023Inventor: KAI-LUNG CHENG
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Patent number: 11474709Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: January 20, 2021Date of Patent: October 18, 2022Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20210318927Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: Parvaneh ALAVI, Kai-Lung CHENG, Yun-Tzuo LAI, Haining LIU
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Patent number: 11086712Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: GrantFiled: November 22, 2019Date of Patent: August 10, 2021Assignee: Western Digital Technologies, Inc.Inventors: Parvaneh Alavi, Kai-Lung Cheng, Yun-Tzuo Lai, Haining Liu
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Patent number: 11048589Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: April 17, 2019Date of Patent: June 29, 2021Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20210141542Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10901632Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 26, 2019Date of Patent: January 26, 2021Assignee: WESTERN DITIGAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20200367534Abstract: Disclosed is a convenient instant tapioca beverage pack including a food convenience package and a beverage container. The food convenience package includes a sealed packaging bag containing a cooked tapioca pearl food, and the cooked tapioca pearl food includes cooked tapioca pearls and a frozen body of a dipping solution. A store staff can tear a tear notch of the packaging bag and heat up the packaging bag, and then pour the cooked tapioca pearl food contained in the packaging bag into the beverage container after heating, and then add a cold or hot liquid to complete the formulation of the pearl milk tea. Therefore, a particulate beverage such as a pearl milk tea can be formulated conveniently and instantly.Type: ApplicationFiled: May 23, 2019Publication date: November 26, 2020Inventor: KAI-LUNG CHENG
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Publication number: 20200089563Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: ApplicationFiled: November 22, 2019Publication date: March 19, 2020Inventors: Parvaneh ALAVI, Kai-Lung CHENG, Yun-Tzuo LAI, Haining LIU
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Patent number: 10496470Abstract: A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.Type: GrantFiled: December 30, 2016Date of Patent: December 3, 2019Assignee: Western Digital Technologies, Inc.Inventors: Parvaneh Alavi, Kai-Lung Cheng, Yun-Tzuo Lai, Haining Liu
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Publication number: 20190347018Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Publication number: 20190251028Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: ApplicationFiled: April 17, 2019Publication date: August 15, 2019Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10379758Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 31, 2017Date of Patent: August 13, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 10289551Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: May 11, 2017Date of Patent: May 14, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20180373445Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: July 31, 2017Publication date: December 27, 2018Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Publication number: 20180329818Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: ApplicationFiled: May 11, 2017Publication date: November 15, 2018Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: D1027651Type: GrantFiled: October 15, 2020Date of Patent: May 21, 2024Assignee: LIAN FA INTERNATIONAL DINING BUSINESS CORPORATIONInventor: Kai-Lung Cheng