Patents by Inventor Kai-Ping Chen
Kai-Ping Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11943373Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.Type: GrantFiled: June 2, 2021Date of Patent: March 26, 2024Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITEDInventors: Mao Cai Li, Zong You Wang, Kai Ban Zhou, Chang Qing Yang, Hu Lan, Li Kong, Jin Song Zhang, Yi Fang Shi, Geng Liang Zhu, Qu Cheng Liu, Qiu Ping Chen
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Patent number: 10672864Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: GrantFiled: March 11, 2019Date of Patent: June 2, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Patent number: 10658368Abstract: A dynamic random access memory (DRAM) includes a first bit line extending along a first direction, a first buried word line extending along a second direction, and an active region overlapping part of the first bit line and part of the first buried word line. Preferably, the active region comprises a V-shape. Moreover, the DRAM also includes at least a storage node contact overlapping one end of the active region, in which the storage node contact includes an ellipse.Type: GrantFiled: December 20, 2017Date of Patent: May 19, 2020Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Wan-Chi Wu, Kai-Ping Chen, Hong-Ru Liu
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Patent number: 10490557Abstract: A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.Type: GrantFiled: March 7, 2018Date of Patent: November 26, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Wei Feng, Ying-Chiao Wang, Chien-Ting Ho, Kai-Ping Chen
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Publication number: 20190206982Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: ApplicationFiled: March 11, 2019Publication date: July 4, 2019Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20190157277Abstract: A dynamic random access memory (DRAM) includes a first bit line extending along a first direction, a first buried word line extending along a second direction, and an active region overlapping part of the first bit line and part of the first buried word line. Preferably, the active region comprises a V-shape. Moreover, the DRAM also includes at least a storage node contact overlapping one end of the active region, in which the storage node contact includes an ellipse.Type: ApplicationFiled: December 20, 2017Publication date: May 23, 2019Inventors: Wan-Chi Wu, Kai-Ping Chen, Hong-Ru Liu
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Patent number: 10290736Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.Type: GrantFiled: January 17, 2018Date of Patent: May 14, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Kai-Ping Chen, Li-Wei Feng, Kuei-Hsuan Yu, Chiu-Hsien Yeh
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Patent number: 10276650Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: GrantFiled: March 21, 2018Date of Patent: April 30, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Patent number: 10181473Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.Type: GrantFiled: March 8, 2017Date of Patent: January 15, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Li-Wei Feng, Ying-Chiao Wang, Tsung-Ying Tsai, Kai-Ping Chen, Chien-Ting Ho
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Patent number: 10157744Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.Type: GrantFiled: February 1, 2018Date of Patent: December 18, 2018Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Kai-Ping Chen, Kuei-Hsuan Yu, Chiu-Hsien Yeh, Li-Wei Feng
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Patent number: 10118909Abstract: The present invention relates to a monascuspurpurone compound of formula (I): or a pharmaceutically acceptable derivative thereof as described in the specification, the process for preparation of the same, and the composition comprising the same. The uses of a monascuspurpurone compound for promoting adipocyte differentiation, for increasing the activity of PPAR? and/or C/EBP?, for lowering blood glucose, for preventing and/or treating a disease or disorder related to insulin resistance, and for preventing and/or treating metabolic syndrome or its complications are also provided.Type: GrantFiled: October 9, 2014Date of Patent: November 6, 2018Inventors: Ming-Jen Cheng, Ping-Hsun Yang, Ming-Der Wu, Shie-Jea Lin, Gwo-Fang Yuan, Yen-Lin Chen, Hsuen-Chun Liao, Kai-Ping Chen
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Publication number: 20180308923Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.Type: ApplicationFiled: March 21, 2018Publication date: October 25, 2018Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Chia-Lung Chang, Jui-Min Lee, Po-Chun Chen, Li-Wei Feng, Ying-Chiao Wang, Wen-Chieh Lu, Chien-Ting Ho, Tsung-Ying Tsai, Kai-Ping Chen
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Publication number: 20180294269Abstract: A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.Type: ApplicationFiled: March 7, 2018Publication date: October 11, 2018Inventors: Li-Wei Feng, Ying-Chiao Wang, Chien-Ting Ho, Kai-Ping Chen
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Publication number: 20180226251Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.Type: ApplicationFiled: February 1, 2018Publication date: August 9, 2018Inventors: Kai-Ping Chen, Kuei-Hsuan Yu, Chiu-Hsien Yeh, Li-Wei Feng
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Publication number: 20180226408Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.Type: ApplicationFiled: March 8, 2017Publication date: August 9, 2018Inventors: Li-Wei Feng, Ying-Chiao Wang, Tsung-Ying Tsai, Kai-Ping Chen, Chien-Ting Ho
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Publication number: 20180212055Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.Type: ApplicationFiled: January 17, 2018Publication date: July 26, 2018Inventors: Kai-Ping Chen, Li-Wei Feng, Kuei-Hsuan Yu, Chiu-Hsien Yeh
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Patent number: 9867857Abstract: A method for inhibiting xanthine oxidase and for reducing uric acid levels using a pharmaceutical composition or a food product obtained by culturing Gluconacetobacter hansenii or Acetobacter pasteurianus in a medium. Also disclosed is a pharmaceutical composition and a food product that each include a metabolite of Gluconacetobacter hansenii or Acetobacter pasteurianus for reducing uric acid levels in a subject and methods for producing the pharmaceutical composition and the food product.Type: GrantFiled: August 19, 2015Date of Patent: January 16, 2018Assignee: Food Industry Research and Development InstituteInventors: Siao-Jhen Cheng, Yen-Lin Chen, Hsun-Yin Hsu, Kai-Ping Chen, Chiao-Ming Liao, Yi-Jen Yech
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Patent number: 9771342Abstract: The present invention relates to a novel monascuspurpurone compound of formula (I): or a pharmaceutically acceptable derivative thereof as described in the specification, the process for preparation of the same, and the composition comprising the same. The uses to of a monascuspurpurone compound for promoting adipocyte differentiation, for increasing the activity of PPAR? and/or C/EBP?, for lowering blood glucose, for preventing and/or treating a disease or disorder related to insulin resistance, and for preventing and/or treating metabolic syndrome or its complications are also provided.Type: GrantFiled: July 10, 2014Date of Patent: September 26, 2017Assignee: Food Industry Research and Development InstituteInventors: Ming-Jen Cheng, Ping-Hsun Yang, Ming-Der Wu, Shie-Jea Lin, Gwo-Fang Yuan, Yen-Lin Chen, Hsuen-Chun Liao, Kai-Ping Chen
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Patent number: 9474774Abstract: The present invention relates to novel pyridine alkaloid compounds of formula (I): or a pharmaceutically acceptable derivative thereof as described in the specification, the process for the preparation of the same, and the composition comprising the same. The uses of a pyridine compound for increasing the activity of PPAR?, for the prevention and/or treatment of a disease or disorder related to insulin resistance, and for the prevention and/or treatment of metabolic syndrome or its complication are also provided. The invention also provides extracts of red yeast-fermented products and their uses for prevention and/or treatment of a disease or disorder related to insulin resistance, such as metabolic syndrome.Type: GrantFiled: December 30, 2010Date of Patent: October 25, 2016Assignee: FOOD INDUSTRY RESEARCH AND DEVELOPMENT INSTITUTEInventors: Ming-Der Wu, Ming-Jen Cheng, Shie-Jea Lin, Chi-Hua Chen, Yen-Lin Chen, Hui-Ping Chen, Kai-Ping Chen, Ping-Shin Yang, Shiow-Wen Chen, Gwo-Fang Yuan
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Patent number: 9441210Abstract: The present invention relates to a method of reducing the level of uric acid in a subject, which comprises administering to said subject an effective amount of a fermentation product of Tenacibaculum sp. Also provided are a method of preventing and/or treating a disease or disorder related to hyperuricemia, a method of increasing the digestion of uric acid and a method of producing uricase.Type: GrantFiled: June 25, 2014Date of Patent: September 13, 2016Assignee: FOOD INDUSTRY RESEARCH AND DEVELOPMENT INSTITUTEInventors: Mei-Huei Chen, Siao-Jhen Chen, Hsun-Yin Hsu, Yen-Lin Chen, Kai-Ping Chen, Yi-Jen Yech, Li-Ting Wang, Hing-Yuen Chan