Patents by Inventor KAI-SHUN HU

KAI-SHUN HU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11188705
    Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: November 30, 2021
    Assignee: Synopsys, Inc.
    Inventors: Tao-Chun Yu, Hsien-Shih Chiu, Shao-Yun Fang, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
  • Publication number: 20200364394
    Abstract: An efficient electronic structure for circuit design, testing and/or manufacture for validating a cell layout design using an intelligent engine trained using selectively arranged cells selected from a cell library. An initial design rule violation (DRV) prediction engine is initially trained using a plurality of pin patterns generated by predefined cell placement combinations, where pin patterns are pixelized and quantified and is classified as either (i) a DRV pin pattern (i.e., pin patterns likely to produce a DRV) or (ii) a DRV-clean pin pattern (i.e., pin patterns unlikely to produce a DRV).
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Inventors: Tao-Chun Yu, Hsien-Shih Chiu, Shao-Yun Fang, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, Henry Sheng
  • Patent number: 9881118
    Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: January 30, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Hsien-Shih Chiu, Kai-Shun Hu
  • Patent number: 9721056
    Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 1, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Hsien-Shih Chiu, Kai-Shun Hu
  • Publication number: 20150278421
    Abstract: A method for routing a circuit device having an array of bump pads includes identifying a routing direction associated with a bump, generating a power strap and a ground strap based on the routing direction, forming a routing channel in accordance with the routing direction, setting a start point and an endpoint in the routing channel, and connecting the start point and the endpoint using a wire within the routing channel. The method further includes placing the start point to a power or ground strap in response to a target power/ground ratio.
    Type: Application
    Filed: December 18, 2014
    Publication date: October 1, 2015
    Inventors: HSIEN-SHIH CHIU, KAI-SHUN HU
  • Publication number: 20150178441
    Abstract: A method for designing an integrated circuit (IC) includes, in part, dividing the wires disposed in the IC into a multitude of segments each having a length extending from a first end point to a second end point. Each segment is then widened without overlapping any adjacent object. As an example, an intermediate, or expanded, segment is formed that includes the first and the second end points and has a size to overlap with an adjacent object. The method includes identifying regions in the adjacent objects that overlap with the expanded segment. For each of the identified regions, an expanded region is formed, which has a shape and size to enclose the identified object with additional spacing around the perimeter. Next, the size of the expanded segment is reduced to form the wide segment such that the wide segment does not overlap any of the adjacent expanded objects.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 25, 2015
    Inventors: HSIEN-SHIH CHIU, KAI-SHUN HU