Patents by Inventor Kai Tian

Kai Tian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230349973
    Abstract: A circuit for controlling calibration includes a process circuit, an off-chip calibration circuit and a mode switching circuit. The process circuit is configured to perform, in a first test mode, a process corner test on the memory to obtain a test result signal, the test result signal being used for determining a process corner parameter. The off-chip calibration circuit is configured to receive and store a first calibration code sent by a controller, the first calibration code being determined by the controller according to a current environment parameter of the memory and the process corner parameter.
    Type: Application
    Filed: February 14, 2023
    Publication date: November 2, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai TIAN, Enpeng GAO, Zengquan WU
  • Publication number: 20230327656
    Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.
    Type: Application
    Filed: August 27, 2022
    Publication date: October 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai TIAN, Ling ZHU
  • Publication number: 20230230636
    Abstract: The present disclosure relates to methods of writing data in nucleic acid chains and methods of reading data written in nucleic acid chains. The present disclosure also relates to a kit for writing and reading data in nucleic acid chains.
    Type: Application
    Filed: May 14, 2021
    Publication date: July 20, 2023
    Inventors: Li-Qun GU, Kai TIAN
  • Patent number: 11676642
    Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: June 13, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Fengqin Zhang, Kangling Ji, Kai Tian, Xianjun Wu
  • Patent number: 11671030
    Abstract: Voltage converter circuits including a first and second branch. The first branch is coupled between a first DC terminal and a second DC terminal and includes a first and second winding around a magnetic core. The first and second winding are coupled to an AC terminal via a common node. The second branch is coupled in parallel to the first branch between the first and second DC terminals and includes a third winding around the magnetic core. The third winding is coupled to the AC terminal such that the first and second branches convert a first voltage into a second voltage. The first, second and third windings are configured to cause magnetic flux generated by a differential mode (DM) component of a first current in the first branch and magnetic flux generated by the DM component of a second current in the second branch to enhance with each other.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: June 6, 2023
    Assignee: ABB Schweiz AG
    Inventors: Kai Tian, Tinho Li, Kuenfaat Yuen, Mei Liang
  • Publication number: 20230170689
    Abstract: An electrostatic protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage dividing unit, where the monitoring unit is connected to at least one probe pad, a discharge unit and a controllable voltage dividing unit, and the monitoring unit is configured to generate a first trigger signal in response to that an electrostatic pulse is present on any probe pad; the discharge unit connected between the at least one probe pad and the ground pad, and configured to form, under control of the first trigger signal, at least one path for discharging electrostatic charges to the ground pad; and the controllable voltage dividing unit is connected to the discharge unit and is configured to share a part of voltage of the first trigger signal for the discharge unit.
    Type: Application
    Filed: July 1, 2022
    Publication date: June 1, 2023
    Inventors: Ling ZHU, Kai TIAN
  • Publication number: 20230136979
    Abstract: An electrostatic protection circuit for a chip including a power supply pad and a ground pad, the electrostatic protection circuit includes: a monitoring assembly, configured to generate a trigger signal when an electrostatic pulse is present on the power supply pad; a discharge transistor connected between the power pad and the ground pad and configured to be turned on under control of the trigger signal to discharge electrostatic charges to the ground pad; and a control circuit connected to the monitoring assembly and configured to control a duration of the trigger signal generated by the monitoring assembly.
    Type: Application
    Filed: July 2, 2022
    Publication date: May 4, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Ling ZHU, Kai TIAN
  • Publication number: 20230023642
    Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a discharge transistor, located between the power supply pad and a ground pad, and configured to be turned on under a control of the trigger signal, so as to discharge an electrostatic charge to the ground pad; and a first controllable voltage division unit, connected to the discharge transistor, and configured to switch an operating mode under a control of a control signal. The operating mode includes a voltage division mode. When operating in the voltage division mode, the controllable voltage division unit is configured to carry a part of a voltage applied by the electrostatic charge to the discharge transistor.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 26, 2023
    Inventors: Ling ZHU, Kai TIAN
  • Publication number: 20230028628
    Abstract: A package structure, a packaging method and a semiconductor device are provided. The method includes: providing a semiconductor functional structure, an interconnecting layer disposed on a surface of the semiconductor functional structure; forming an isolation layer exposing part of the interconnecting layer, the exposed part of the interconnecting layer acting as a first pad, and the first pad used for performing a first type test; after completing the first type test, forming a redistribution layer on the first pad and the isolation layer, the redistribution layer and the interconnecting layer electrically connected; and forming a first insulating layer exposing parts of the redistribution layer, the exposed parts of the redistribution layer acting as a second pad and a third pad, the second pad used for performing a second type test, and the third pad used for executing a functional interaction corresponding to contents of the second type test.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 26, 2023
    Inventors: Kai TIAN, Hongwen Li, Liang Chen, Wei Jiang, Mengfan Li
  • Publication number: 20230009631
    Abstract: The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.
    Type: Application
    Filed: June 16, 2022
    Publication date: January 12, 2023
    Inventors: Ling ZHU, Kai TIAN
  • Publication number: 20230007947
    Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 12, 2023
    Inventors: Ling ZHU, Kai TIAN
  • Publication number: 20230005851
    Abstract: A packaging structure, a method for manufacturing the same and a semiconductor device are provided. The packaging structure includes a redistribution layer electrically connected with an interconnection layer of a semiconductor functional structure, and an insulating layer covering and exposing part of the redistribution layer. The exposed part of the redistribution layer includes at least one first pad. The first pad includes a first area and a second area arranged continuously. The first area is configured for testing. The second area is configured for performing functional interaction corresponding to content of the test.
    Type: Application
    Filed: September 7, 2022
    Publication date: January 5, 2023
    Inventors: Kai TIAN, Liang CHEN, Mingxing ZUO
  • Publication number: 20220352876
    Abstract: Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventors: Yuxia WANG, Kai TIAN
  • Patent number: 11476771
    Abstract: A system and a method for power conversion. The system includes a rectifier; an inverter; a DC-link capacitor coupled between the rectifier and the inverter; and a controller. The controller is configured to obtain a current value at an output of the inverter and a voltage value across the DC-link capacitor, determine an average component and a fluctuating component of an output voltage of the inverter based on the obtained current value and the voltage value, and determine a current reference for controlling the rectifier based on the average component and the fluctuating component of the output voltage.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: October 18, 2022
    Assignee: ABB SCHWEIZ AG
    Inventors: Ke Dai, Derong Lin, Chengjing Li, Tian Tan, Tinho Li, Kai Tian
  • Publication number: 20220292246
    Abstract: An oscillator layout includes: a first row layout region constituted by sequentially arranging a second B layout region, second A layout region, third B layout region and third A layout region in parallel; and a second row layout region constituted by sequentially arranging a first A layout region, first B layout region, fourth A layout region and fourth B layout region in parallel. Inputs and outputs of the first A layout region, second A layout region, third A layout region and fourth A layout region constitute a first ring topology, inputs and outputs of the first B layout region and third B layout region constitute a second ring topology, inputs and outputs of the second B layout region and fourth B layout region constitute a third ring topology, the second ring topology and third ring topology are both electrically connected to the first ring topology.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yuxia WANG, Kai TIAN
  • Patent number: 11418106
    Abstract: An apparatus for conversion between AC power and DC power. The apparatus includes: a first power conversion circuit having a first AC side and a DC side, at least one second power conversion circuit each having a second AC side and sharing the DC side with the first power conversion circuit, and at least one choke having a first terminal, a second terminal and at least one third terminal, wherein: the first terminal is arranged to be electrically coupled to a phase of the AC power, and the second terminal and the at least one third terminal are electrically coupled to respective same phases of the first AC side of the first power conversion circuit and the second AC side of the at least one second power conversion circuit.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: August 16, 2022
    Assignee: ABB SCHWEIZ AG
    Inventors: Kai Tian, Tinho Li, Kuenfaat Yuen, Mei Liang
  • Patent number: 11398270
    Abstract: The present disclosure provides an input buffer circuit, an intelligent optimization method, and a semiconductor memory thereof. The input buffer circuit may include a detection circuit, a mode control circuit, a double-end differential circuit, and a single-end complementary metal oxide semiconductor (CMOS) unit. The detection circuit may be configured to obtain a working frequency of a chip. The mode control circuit is connected to the detection circuit, and configured to control, according to the working frequency obtained by the detection circuit, an input buffer to enter a double-end differential input mode and a single-end CMOS input mode. The double-end differential circuit and the single-end CMOS circuit are connected to the mode control circuit. The double-end differential input circuit may be configured to process high-speed data transmission in the double-end differential input mode.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 26, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Kai Tian
  • Patent number: 11380368
    Abstract: The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 5, 2022
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: KangLing Ji, Hongwen Li, Kai Tian
  • Publication number: 20220130439
    Abstract: A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.
    Type: Application
    Filed: September 19, 2021
    Publication date: April 28, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai TIAN, Yuxia WANG
  • Publication number: 20220130440
    Abstract: A memory includes: a clock generation circuit, configured to generate a first oscillation signal and a second oscillation signal. The first oscillation signal and the second oscillation signal have a same frequency but opposite phases, and a duty cycle of the first oscillation signal and a duty cycle of the second oscillation signal are both within a first preset range. The memory further includes a differential input circuit, which is configured to receive a first external signal and a second external signal, and generate a first internal signal and a second internal signal. The clock generation circuit is configured to monitor the duty cycle of the first internal signal or the duty cycle of the second internal signal, and enable the duty cycle of the first internal signal or the duty cycle of the second internal signal to be within a second preset range.
    Type: Application
    Filed: September 26, 2021
    Publication date: April 28, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Kai TIAN, Yuxia WANG