Patents by Inventor Kai-Yu Lin
Kai-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240171128Abstract: Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.Type: ApplicationFiled: January 26, 2024Publication date: May 23, 2024Inventors: Sanjeev Jain, Haoran Yu, Nan Sen Lin, Gregory Edward Babcock, Kai Jiang, Hassan Sarbishaei
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Patent number: 11983267Abstract: A data processing method based on Trojan circuit detection includes controlling a processor, in a testing stage, to perform following steps: obtaining a plurality of characteristic values corresponding to a logic gate circuit; performing a distribution adjustment operation on the characteristic values to generate a plurality of adjusted characteristic values; and performing classification on the adjusted characteristic values to generate a logic identification result.Type: GrantFiled: November 30, 2021Date of Patent: May 14, 2024Assignee: INSTITUTE FOR INFORMATION INDUSTRYInventors: Jian Wei Liao, Ting Yu Lin, Kai Chiang Wu, Jung Che Tsai
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Publication number: 20240138059Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a first dielectric layer, pads, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A top surface of the first dielectric layer is higher than an upper surface of each pad. The first metal layer is disposed on a first surface of the first dielectric layer. The second dielectric layer has second openings exposing part of the first metal layer. The second metal layer extends into the second openings and is electrically connected to the first metal layer. The third dielectric layer has third openings exposing part of the second metal layer. The surface treatment layer is disposed on the upper surfaces.Type: ApplicationFiled: November 23, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Kai-Ming Yang, Chia-Yu Peng, Cheng-Ta Ko, Pu-Ju Lin
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Publication number: 20240138063Abstract: A circuit board structure includes a carrier, a thin film redistribution layer disposed on the carrier, solder balls electrically connected to the thin film redistribution layer and the carrier, and a surface treatment layer. The thin film redistribution layer includes a plurality of pads, a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer, and a third dielectric layer. A plurality of first openings of the first dielectric layer expose part of the pads, and a first surface of the first dielectric layer is higher upper surfaces of the pads. The solder balls are disposed in a plurality of third openings of the third dielectric layer and are electrically connected to the second metal layer and the carrier. The surface treatment layer is disposed on the upper surfaces, and a top surface of the surface treatment layer is higher than the first surface.Type: ApplicationFiled: November 15, 2022Publication date: April 25, 2024Applicant: Unimicron Technology Corp.Inventors: Ping-Tsung Lin, Kai-Ming Yang, Chia-Yu Peng, Pu-Ju Lin, Cheng-Ta Ko
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Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
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Publication number: 20240128219Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
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Patent number: 11943877Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.Type: GrantFiled: March 2, 2022Date of Patent: March 26, 2024Assignee: Unimicron Technology Corp.Inventors: Wen-Yu Lin, Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Guang-Hwa Ma, Tzyy-Jang Tseng
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Publication number: 20240097011Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
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Patent number: 11923808Abstract: Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.Type: GrantFiled: January 23, 2023Date of Patent: March 5, 2024Assignee: Skyworks Solutions, Inc.Inventors: Sanjeev Jain, Haoran Yu, Nan Sen Lin, Gregory Edward Babcock, Kai Jiang, Hassan Sarbishaei
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Publication number: 20140316828Abstract: A computing device exchanges electronic tickets between a first client device and a second client device. The computing device notifies the first client device and the second client device to confirm match success information when first ticket information of the first client device matches second ticket information of the second client device, and second ticket information of the first client device matches first ticket information of the second client device.Type: ApplicationFiled: April 22, 2014Publication date: October 23, 2014Applicant: FIH (Hong Kong) LimitedInventor: Kai-Yu Lin
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Publication number: 20110158417Abstract: A communication device with an audio database comprises an audio receiving module, a locator module, an audio identification module and a notification module. The audio receiving module calculates the strength of the at least one signal, the locator module determines whether each of the strength exceeds a predefined value and determines the directionality of the at least one audio signal in accordance with the strength of the at least one audio signal. The audio identification module compares the audio signal with audio modules in accordance with characteristics parameter to issue a warning.Type: ApplicationFiled: November 4, 2010Publication date: June 30, 2011Applicant: FOXCONN COMMUNICATION TECHNOLOGY CORP.Inventor: KAI-YU LIN
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Patent number: 7491421Abstract: A graphite base is made by: mixing nanometered graphite powder with a bonding agent to form a graphite mixture and then grinding the graphite mixture and processing the graphite mixture into a graphite mass with a high pressure by means of hot press, cold press and vibration, and then dipping the graphite mass in a liquid phase asphalt, and then baking the graphite mass to a dry state graphite block. The dry state graphite block is further coated with a layer of metal coating and bonded with metal radiation fins to form a heat sink.Type: GrantFiled: April 13, 2005Date of Patent: February 17, 2009Inventors: Kai-Yu Lin, Yi-Ning Chung
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Publication number: 20090015134Abstract: A light emitting module includes a graphite base having a metal bearing surface at one side, a circuit board bonded to the metal bearing surface of the graphite base and having mounting through holes and a circuit layout, and light emitting devices each having a substrate carrying a light emitting chip and mounted in one mounting through hole of the circuit board and kept in contact with the metal bearing surface of the graphite base for transferring heat energy produced during light emitting operation to the graphite base for quick dissipation and two conducting legs electrically connected with the light emitting chip and respectively extended out of the substrate and electrically bonded to the circuit layout of the circuit board.Type: ApplicationFiled: July 13, 2008Publication date: January 15, 2009Inventor: Kai-Yu Lin
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Publication number: 20060230615Abstract: A graphite base is made by: mixing nanometered graphite powder with a bonding agent to form a graphite mixture and then grinding the graphite mixture and processing the graphite mixture into a graphite mass with a high pressure by means of hot press, cold press and vibration, and then dipping the graphite mass in a liquid phase asphalt, and then baking the graphite mass to a dry state graphite block. The dry state graphite block is further coated with a layer of metal coating and bonded with metal radiation fins to form a heat sink.Type: ApplicationFiled: April 13, 2005Publication date: October 19, 2006Inventors: Kai-Yu Lin, Yi-Ning Chung