Abstract: A detection system for a SlimSAS slot and a method thereof are disclosed. In the detection system, a detecting device generates and transmits a detection signal to a TAP controller; the TAP controller converts the received detection signal into a detection signal in JTAG format, and transmits the detection signal in JTAG format to a CPLD chip and a controllable power module chip of a detection card and/or a boundary scan chip of a circuit board; a detection can be performed on the SMBus pins, the differential signal receiving pins, the differential signal transmitting pins, the clock pins, the sideband pins and the ground pins of the SlimSAS connection interface through the boundary scan chip, the HCSL to LVDS module chip, the IIC chip and the CPLD chip. Therefore, the technical effect of improving slot stability and detection coverage of a SlimSAS slot detection can be achieved.

Abstract: A three-section synchronous slide rail, which has simple structure, longer service life, is easy to install and replace is provided, which includes: two sets of slide rail assemblies which comprise a fixed rail, a middle rail and a sliding rail, synchronization components comprising a flexible deflector unit and a roller, the flexible deflector unit is connected with the fixed rail and the sliding rail, the middle rail is connected with a rope base, a first end of the flexible deflector unit is wound around a first end of the rope base and fixed to the rope base, and a second end of the flexible deflector unit bypasses the roller and is reversely wound on a second end of the rope base and the second end of the flexible deflector unit is fixed to the rope base, a connecting rod is connected between the rope bases.

Abstract: The present invention discloses a superconducting nanowire single photon detector, comprises an arced fractal nanowire structure and the optical cavity structure; the arced fractal nanowire structures being used to alleviate the current-crowding effect and realize that the detection efficiency is insensitive to the polarization states of incident photons, and the arced fractal nanowire structures including parallel-connected arced fractal nanowires and serial-connected arced fractal nanowires; the optical cavity structure being used to achieve simultaneous optimization of the internal quantum efficiency and the absorption efficiency. The invention can be widely used in many fields such as optical communication, single-photon imaging, fluorescence detection, quantum optics, etc. The excellent performance of the detector can significantly promote the development and progress of these fields.

Abstract: Embodiments for forming improved bipolar transistors are provided, manufacturable by a CMOS IC process. The improved transistor comprises an emitter having first and second portions of different depths, a base underlying the emitter having a central portion of a first base width underlying the first portion of the emitter, a peripheral portion having a second base width larger than the first base width partly underlying the second portion of the emitter, and a transition zone of a third base width and lateral extent lying laterally between the first and second portions of the base, and a collector underlying the base. The gain of the transistor is larger than a conventional bipolar transistor made using the same CMOS process. By adjusting the lateral extent of the transition zone, the properties of the improved transistor can be tailored to suit different applications without modifying the underlying CMOS IC process.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: A method for programming a MLC memory includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL?K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL?K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Abstract: Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+?VD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.

Abstract: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method includes (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL?K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Abstract: A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

Abstract: A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises (a) programming the bits of the memory having a Vt level lower than the PV level of a targeted programmed state into programmed bits by using a Vd bias BL; (b) ending this method if each bit of the memory has a Vt level not lower than the PV level of the targeted programmed state, otherwise, continuing the step (c); and (c) setting BL=BL+K1 and repeating the step (a) if each of the programmed bits has a Vt level lower than the PV level, while setting BL=BL?K2, and repeating the step (a) if at least one of the programmed bits has a Vt level not lower than the PV level.

Abstract: Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+?VD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.

Abstract: A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

Abstract: A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

Abstract: A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.