Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

Abstract: A clock circuit. The clock circuit includes a phase detector and an output unit. The phase detector is coupled to receive a reference clock signal and an output clock signal, and is configured to provide a phase signal indicative of a phase difference between the reference and output clock signals. The output unit is configured to provide the output clock signal, and is coupled to a first supply voltage node and a second supply voltage node. The output unit includes a biasing circuit and a voltage-controlled element. The biasing circuit is coupled to receive a control voltage based on the phase signal and is configured to generate a bias voltage based on the received control voltage. The voltage-controlled element is configured to adjust a parameter of the output clock signal based on the bias voltage. A supply-independent output clock is attained using this configuration.

Abstract: An apparatus that minimizes phase error and jitter in a phase-locked loop. The apparatus includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, which are coupled together to form a phase-locked loop. The charge pump within the phase-locked loop contains a pull-up network and a pull-down network which are coupled to each other, and a current compensation device. If the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through the pull-up network and through the pull-down network such that the currents are substantially equal. This ensures that very little current flows into the loop filter, thereby substantially minimizing a build-up of charge on a capacitor in the loop filter, which can cause phase error and jitter in the phase-locked loop.

Abstract: A CPU clock signal generated from a phase lock loop (PLL) circuit and a feedback signal of the PLL circuit are used in generating a JBUS clock signal. The CPU clock signal and the feedback signal include the same amount of static phase offset introduced by the PLL circuit. The CPU clock signal and the feedback signal are input to an alignment detection circuit and used in generating the JBUS clock signal. In one embodiment, the JBUS clock signal is generated in synchronization with the CPU clock signal and having the frequency of the feedback signal. The present invention reduces or eliminates misalignment of the leading edge of the JBUS signal with reference to a specific leading edge of the CPU clock signal due to the presence of static phase offset introduced by the PLL circuit.

Abstract: A CPU clock signal generated from a phase lock loop (PLL) circuit and a feedback signal of the PLL circuit are used in generating a JBUS clock signal. The CPU clock signal and the feedback signal include the same amount of static phase offset introduced by the PLL circuit. The CPU clock signal and the feedback signal are input to an alignment detection circuit and used in generating the JBUS clock signal. In one embodiment, the JBUS clock signal is generated in synchronization with the CPU clock signal and having the frequency of the feedback signal. The present invention reduces or eliminates misalignment of the leading edge of the JBUS signal with reference to a specific leading edge of the CPU clock signal due to the presence of static phase offset introduced by the PLL circuit.