Abstract: Field effect transistor structures include a channel region formed in a recessed portion of a substrate. The recessed channel portion permits the use of relatively thicker source/drain regions thereby providing lower source/drain extension resistivity while maintaining the physical separation needed to overcome various short channel effects. The surface of the recessed channel portion may be of a rectangular, polygonal, or curvilinear shape. In a further aspect of the present invention, transistors are manufactured by a process in which a damascene layer is patterned, the channel region is recessed by etch that is self-aligned to the patterned damascene layer, and the gate electrode is formed by depositing a material over the channel region and patterned damascene layer, polishing off the excess gate electrode material and removing the damascene layer.

Abstract: A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown.

Abstract: A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs.

Abstract: An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors.

Abstract: An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors.