Abstract: Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool. According to one embodiment of the present invention cells of a circuit design are placed in a placement of an integrated circuit, and wires are routed between the cells to complete a layout of the integrated circuit having a number of nets. The placement is analyzed for timing performance, and an improved location is identified for each cell in the placement. The improved location is identified based on an estimated savings in delays caused by all of the nets in the layout to a signal propagating through the layout when the cell is placed in the improved location and a net criticality of each net in the layout.