Patents by Inventor Kalpana Vakati

Kalpana Vakati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907066
    Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Lakshmi Kalpana Vakati, Harish R. Singidi
  • Publication number: 20240045616
    Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.
    Type: Application
    Filed: August 5, 2022
    Publication date: February 8, 2024
    Inventors: Kishore Kumar Muchherla, Lakshmi Kalpana Vakati, Dave Scott Ebsen, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Jiangli Zhu, Fangfang Zhu, Akira Goda
  • Publication number: 20240028259
    Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Inventors: Kishore Kumar Muchherla, Peter Feeley, Jiangli Zhu, Fangfang Zhu, Akira Goda, Lakshmi Kalpana Vakati, Vivek Shivhare, Dave Scott Ebsen, Sanjay Subbarao
  • Publication number: 20240029815
    Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Kishore Kumar Muchherla, Akira Goda, Dave Scott Ebsen, Lakshmi Kalpana Vakati, Jiangli Zhu, Peter Feeley, Sanjay Subbarao, Vivek Shivhare, Fangfang Zhu
  • Publication number: 20230367680
    Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.
    Type: Application
    Filed: May 5, 2023
    Publication date: November 16, 2023
    Inventors: Lu Tong, Ashish Ghai, Chai Chuan Yao, Ekamdeep Singh, Lakshmi Kalpana Vakati, Sheng Huang Lee, Matthew Ivan Warren, Dheeraj Srinivasan, Jeffrey Ming-Hung Tsai
  • Publication number: 20230305744
    Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 28, 2023
    Inventors: Kishore Kumar Muchherla, Eric N. Lee, Jeffrey S. McNeil, Jonathan S. Parry, Lakshmi Kalpana Vakati
  • Publication number: 20220261313
    Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.
    Type: Application
    Filed: May 2, 2022
    Publication date: August 18, 2022
    Inventors: Xiangang Luo, Jianmin Huang, Lakshmi Kalpana Vakati, Harish R. Singidi
  • Patent number: 10249382
    Abstract: Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: April 2, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Dana Lee, Ekam Singh, Ashish Ghai, Kalpana Vakati
  • Publication number: 20190066818
    Abstract: Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.
    Type: Application
    Filed: August 22, 2017
    Publication date: February 28, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Dana Lee, Ekam Singh, Ashish Ghai, Kalpana Vakati
  • Publication number: 20190006021
    Abstract: A leakage current detection circuit is configured to perform an inter-block leakage current detection process to detect for leakage current between a select gate bias line associated with a first block and one or more word lines associated with a second block. During a time period, a first switching circuit may bias the select gate bias line of the first block with a first leakage detection voltage, and a second switching circuit may bias the word lines of the second block with a second leakage detection voltage. During this time period, a current sensing circuit may sense for leakage current in a global select gate bias line.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Gopinath Balakrishnan
  • Publication number: 20180061505
    Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Chang Siau, Gopinath Balakrishnan, Kapil Verma
  • Patent number: 9905307
    Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Chang Siau, Gopinath Balakrishnan, Kapil Verma
  • Patent number: 9711227
    Abstract: To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Yuvaraj Krishnamoorthy, Ekamdeep Singh, Kalpana Vakati, Maythin Uthayopas, Mark Shlick, Srikar Peesari
  • Patent number: 8705290
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: April 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Prashant S. Damle, Krishna K. Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
  • Publication number: 20130016569
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 17, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
  • Patent number: 8331160
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
  • Publication number: 20110280085
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 17, 2011
    Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
  • Patent number: 7990772
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: August 2, 2011
    Assignee: Micron Technology Inc.
    Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda
  • Publication number: 20100232234
    Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 16, 2010
    Inventors: Prashant S. Damle, Krishna Parat, Alessandro Torsi, Carlo Musilli, Kalpana Vakati, Akira Goda