Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: In an embodiment, a circuit configured for asymmetric ageing prevention in an integrated circuit (IC) comprises a primary clock configured to generate a primary clock signal, a secondary clock configured to generate a secondary clock signal, a state determination circuit, and a control circuit. The state determination circuit is configured to determine a current operating state associated with at least one of a primary clock condition and a power-on-reset condition in the IC. The control circuit is configured to generate a control signal in response to a determination of an first operating state. The control signal is configured to facilitate a transition from the primary clock to the secondary clock upon determination of the first operating state, and a transition from a safe operating mode to a normal operating mode upon determination of a second operating state. The secondary clock is associated with a safe operating mode of the IC.

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract: The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.