Abstract: A semiconductor substrate has at least one PN junction with dopant atoms at the junction. A non-dopant at the junction provides interstitial traps to prevent diffusion during annealing. In a process for making this, a non-dopant diffusion barrier, e.g., C, N, Si, F, etc., is implanted into the “halo” region of a semiconductor device, e.g. diode, bipolar transistor, or CMOSFET. This combined with a lower annealing budget (“Spike Annealing”) allows a steeper halo dopant profile to be generated. The invention is especially useful in CMOSFETs with gate lengths less than about 50 nm.

Abstract: A method and circuit are provided for color space conversion of Y (luminance) and UV (chrominance) components from a planar YUV 4:2:0 format to an interleaved, or packed YUV 4:2:2 format, and from an interleaved, or packed YUV 4:2:2 format to a planar YUV 4:2:0 format. The method for both conversions includes reading source data, interpolating the sampled YUV component values, and performing a pass to thereby write the converted YUV component values in three passes, one pass for all values of the respective YUV components.

Abstract: A process of fabricating a CMOS device having an enhanced ultra-shallow junction in which substantially no transient enhanced diffusion of dopant occurs is provided. Specifically, the CMOS device having the aforementioned properties is formed by implanting a dopant into a surface of a Si-containing substrate so as to form a doped region therein; forming a metal layer on the Si-containing substrate; and heating the metal layer so as to convert the metal layer into a metal silicide layer while simultaneously activating the doped region, whereby vacancies created by this heating step combine with interstitials created in step (a) so as to substantially eliminate any transient diffusion of the dopant in said Si-containing substrate.

Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.

Abstract: A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.

Abstract: A method for fabricating an ultra-shallow semiconductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Abstract: The present invention is directed to a method of forming a new material layer or region near an interface region of two dissimilar materials, and an optional third layer, wherein at least one of said dissimilar materials or optional third is capable of being heated by microwave energy. The method of the present invention includes a step of irradiating a structure containing at least two dissimilar materials and an optional third layer under conditions effective to form the new material layer in the structure. An apparatus for conducting the microwave heating as well as the structures formed from the method are also described herein.

Abstract: Excimer laser annealing is employed to improve the flexibility of gate activation and source/drain activation as well as to limit the extent of decomposition of a high dielectric constant storage capacitor in fabricating trench storage semiconductor memory devices.

Abstract: A rapid thermal processing apparatus and a method of using such apparatus for the continuous heat treatment of at least one workpiece, which apparatus includes a cavity of generally elongated shape, a process chamber defined by interior walls inside the cavity, a device for delivering, regulating and extracting process gases from the chamber, a device for transporting at least one workpiece through the chamber in a substantially forward direction, a device for heating at least a section of the chamber, and a device for cooling the at least one workpiece downstream from the heating device. The cavity for the apparatus may also be provided in either a curved or a linear configuration for carrying out the present invention method.

Abstract: A rapid thermal processing apparatus and a method of using such apparatus for the continuous heat treatment of at least one workpiece, which apparatus includes a cavity of generally elongated shape, a process chamber defined by interior walls inside the cavity, a device for delivering, regulating and extracting process gases from the chamber, a device for transporting at least one workpiece through the chamber in a substantially forward direction, a device for heating at least a section of the chamber, and a device for cooling the at least one workpiece downstream from the heating device. The cavity for the apparatus may also be provided in either a curved or a linear configuration for carrying out the present invention method.

Abstract: The present invention is a method of utilizing microwave energy for annealing of ion implanted wafers. By controlling the time, power density and temperature regime, it is possible to substantially fully anneal the wafer while limiting (and substantially preventing) the diffusion of dopant into the silicon, thereby producing higher performance scaled semiconductor devices. It is also possible, using different conditions, to allow and control the dopant profile (diffusion) into the silicon. Another aspect of the present invention is a method of forming a PN junction in a semiconductor wafer having a profile depth less than about 50 nm and a profile wherein the net doping concentration at said PN junction changes by greater than about one order of magnitude over 6 nm wherein the surface concentration of said dopant is greater than about 1×1020/cm3.

Abstract: A rapid thermal processing apparatus and a method of using such apparatus for the continuous heat treatment of at least one workpiece, which apparatus includes a cavity of generally elongated shape, a process chamber defined by interior walls inside the cavity, a device for delivering, regulating and extracting process gases from the chamber, a device for transporting at least one workpiece through the chamber in a substantially forward direction, a device for heating at least a section of the chamber, and a device for cooling the at least one workpiece downstream from the heating device. The cavity for the apparatus may also be provided in either a curved or a linear configuration for carrying out the present invention method.

Abstract: A pipeline apparatus for processing 3D graphics data will be described. The pipeline apparatus includes a first request memory to fetch information corresponding to a texture operand. A second request memory fetches information responding to a color operand and Z operand. A control circuit coordinates data flow from the first request memory and the second request memory into a memory channel by preventing the number of requests from the first request memory from exceeding by a predetermined number, the number of requests from the second request memory. By properly coordinating the data flow, deadlock of a data fetching pipeline is avoided.

Abstract: The present invention is directed to a method of forming a new material layer or region near an interface region of two dissimilar materials, and an optional third layer, wherein at least one of said dissimilar materials or optional third is capable of being heated by microwave energy. The method of the present invention includes a step of irradiating a structure containing at least two dissimilar materials and an optional third layer under conditions effective to form the new material layer in the structure. An apparatus for conducting the microwave heating as well as the structures formed from the method are also described herein.

Abstract: The present invention is a method of utilizing microwave energy for annealing of ion implanted wafers. By controlling the time, power density and temperature regime, it is possible to substantially fully anneal the wafer while limiting (and substantially preventing) the diffusion of dopant into the silicon, thereby producing higher performance scaled semiconductor devices. It is also possible, using different conditions, to allow and control the dopant profile (diffusion) into the silicon. Another aspect of the present invention is a method of forming a PN junction in a semiconductor wafer having a profile depth less than about 50 nm and a profile wherein the net doping concentration at said PN junction changes by greater than about one order of magnitude over 6 nm wherein the surface concentration of said dopant is greater than about 1.times.10.sup.20 /cm.sup.3.

Abstract: A method for fabricating an ultra-shallow semi-conductor junction using a high energy co-implantation step; a low energy dopant implantation step, and a fast isothermal annealing step is provided. Microelectronics devices such as FET and CMOS devices containing said ultra-shallow semiconductor junction is also provided herein.

Abstract: A disk drive controller which can be programmed for compatibility with a variety of disk drives having differing interface requirements. Information regarding specific characteristics of a disk drive to be installed is loaded into a register in the disk drive controller. Information such as the drives data rate, density, precompensation, physical designation, and mode of operation of a disk drive can be programmed into the register. The interface between the disk drive controller and the disk drive is then configured according to the stored information.

Abstract: There is provided an improved process for enhanced LAK cell activation wherein the peripheral blood mononuclear cells are treated with an amino acid amide to yield depletion, prior to the lymphocytes being cultured at high density. Also provided are pharmaceutical compositions and methods of using them in combination with IL-2 to treat cancer in a mammal.

Abstract: A system for inspection of substrates and circuit devices employing a retarding field in an E-beam to reduce the incident beam energy to the crossover point at which minimum substrate charging occurs. This selectively separates backscattered electrons from secondary electrons emitted from the sample surface. An E-beam is columnated and directed through a bias plate and annular detector on a sample held at a negative bias with respect to the detector and the plate. The negative bias is selected so that the incident beam strikes the substrate at the crossover energy to permit collection of backscattered electrons. This selective detection generates a sharp image of the sample surface.