Patents by Inventor Kamalesh Srivastava
Kamalesh Srivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090197114Abstract: A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead free solder selected from the group comprising Sn—Ag—Cu solder and Sn—Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 to 2.0% by weight Sb or Bi, and 0.5 to 3.0% Ag. Formation of voids at an interface between the solder and the solder capture pad is suppressed, by including Zn. Interlayer dielectric delamination is suppressed, and electromigration characteristics are greatly improved. Methods for forming solder joints using the solders.Type: ApplicationFiled: October 20, 2008Publication date: August 6, 2009Inventors: Da-Yuan Shih, Donald W. Henderson, Sung K. Kang, Minhua Lu, Jae-Woong Nah, Kamalesh Srivastava
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Publication number: 20090197103Abstract: A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead free solder selected from the group comprising Sn—Ag—Cu solder and Sn—Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 to 2.0% by weight Sb or Bi, and 0.5 to 3.0% Ag. Formation of voids at an interface between the solder and the solder capture pad is suppressed, by including Zn. Interlayer dielectric delamination is suppressed, and electromigration characteristics are greatly improved. Methods for forming solder joints using the solders.Type: ApplicationFiled: October 20, 2008Publication date: August 6, 2009Inventors: Da-Yuan Shih, Donald W. Henderson, Sung K. Kang, Minhua Lu, Jae-Woong Nah, Kamalesh Srivastava
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Publication number: 20070080455Abstract: A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.Type: ApplicationFiled: October 11, 2005Publication date: April 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Donna Zupanski-Nielsen, William Landers, Ian Melville, Roger Quon, Timothy Daubenspeck, Kamalesh Srivastava, Mary Cullinan-Scholl, Lawrence Clevenger, Christopher Muzzy
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Publication number: 20060249854Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.Type: ApplicationFiled: June 29, 2006Publication date: November 9, 2006Inventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Samuel McKnight, Kevin Petrarca, Kamalesh Srivastava, Roger Quon
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Publication number: 20060081981Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: November 10, 2005Publication date: April 20, 2006Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Publication number: 20060009022Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: ApplicationFiled: September 12, 2005Publication date: January 12, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamalesh Srivastava, Subhash Shinde, Tien-Jen Cheng, Sarah Knickerbocker, Roger Quon, William Sablinski, Julie Biggs, David Eichstadt, Jonathan Griffith
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Publication number: 20050208748Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.Type: ApplicationFiled: March 17, 2004Publication date: September 22, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kamalesh Srivastava, Subhash Shinde, Tien-Jen Cheng, Sarah Knickerbocker, Roger Quon, William Sablinski, Julie Biggs, David Eichstadt, Jonathan Griffith
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Publication number: 20050167837Abstract: A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.Type: ApplicationFiled: January 21, 2004Publication date: August 4, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Samuel McKnight, Kevin Petrarca, Kamalesh Srivastava, Roger Quon
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Publication number: 20050103636Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.Type: ApplicationFiled: November 18, 2003Publication date: May 19, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tien-Jen Cheng, David Eichstadt, Jonathan Griffith, Sarah Knickerbocker, Rosemary Previti-Kelly, Roger Quon, Kamalesh Srivastava, Keith Wong
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Publication number: 20050062170Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: International Business Machines CorporationInventors: Julie Biggs, Tien-Jen Cheng, David Eichstadt, Lisa Fanti, Jonathan Griffith, Randolph Knarr, Sarah Knickerbocker, Kevin Petrarca, Roger Quon, Wolfgang Sauter, Kamalesh Srivastava, Richard Volant
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Patent number: 6727589Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: November 30, 2000Date of Patent: April 27, 2004Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6479884Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: June 29, 2001Date of Patent: November 12, 2002Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6348736Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. A first protective layer is formed in situ on the dielectric material, such as by exposing the material to an oxygen-containing or flourine containing plasma. Also, by performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. The first protective layer and the surface protective covering can be formed by essentially identical processes.Type: GrantFiled: October 29, 1999Date of Patent: February 19, 2002Assignee: International Business Machines CorporationInventors: Vincent J. McGahay, John P. Hummel, Joyce Liu, Rebecca Mih, Kamalesh Srivastava, Robert Cook, Stephen E. Greco
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Patent number: 6329280Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: GrantFiled: May 13, 1999Date of Patent: December 11, 2001Assignee: International Business Machines CorporationInventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010036739Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.Type: ApplicationFiled: June 29, 2001Publication date: November 1, 2001Inventors: Robert Cook, Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Patent number: 6221780Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.Type: GrantFiled: September 29, 1999Date of Patent: April 24, 2001Assignee: International Business Machines CorporationInventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava
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Publication number: 20010000115Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer nay be either a single damascene or a dual damascene layer.Type: ApplicationFiled: November 30, 2000Publication date: April 5, 2001Inventors: Stephen E. Greco, John P. Hummel, Joyce Liu, Vincent J. McGahay, Rebecca Mih, Kamalesh Srivastava