Patents by Inventor Kambiz Samadi
Kambiz Samadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11004780Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.Type: GrantFiled: November 19, 2019Date of Patent: May 11, 2021Assignee: QUALCOMM IncorporatedInventors: Kambiz Samadi, Shreepad Amar Panth, Yang Du, Robert Philip Gilmore
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Publication number: 20200105652Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.Type: ApplicationFiled: November 19, 2019Publication date: April 2, 2020Inventors: Kambiz Samadi, Shreepad Amar Panth, Yang Du, Robert Philip Gilmore
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Patent number: 10510651Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.Type: GrantFiled: December 14, 2018Date of Patent: December 17, 2019Assignee: QUALCOMM IncorporatedInventors: Kambiz Samadi, Shreepad Amar Panth, Yang Du, Robert Philip Gilmore
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Publication number: 20190259677Abstract: A device comprising a first die, a second die coupled to a first die, and a polymer planarization layer. The second die includes a side portion and a backside portion. The polymer planarization layer is coupled to the first die and the second die such that the polymer planarization layer is coupled to the side portion and the backside portion of the second die. The polymer planarization layer includes an organic polymer. The polymer planarization layer may include a self planarizing material.Type: ApplicationFiled: September 19, 2018Publication date: August 22, 2019Inventors: Jon LASITER, Ravindra Vaman SHENOY, Kambiz SAMADI, Jing XIE
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Publication number: 20190122973Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.Type: ApplicationFiled: December 14, 2018Publication date: April 25, 2019Inventors: Kambiz Samadi, Shreepad Amar Panth, Yang Du, Robert Philip Gilmore
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Patent number: 10192813Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.Type: GrantFiled: January 29, 2013Date of Patent: January 29, 2019Assignee: QUALCOMM IncorporatedInventors: Kambiz Samadi, Shreepad A. Panth, Yang Du, Robert P. Gilmore
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Publication number: 20190027435Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.Type: ApplicationFiled: September 27, 2018Publication date: January 24, 2019Inventors: Pratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du
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Patent number: 10176147Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC.Type: GrantFiled: March 7, 2017Date of Patent: January 8, 2019Assignee: QUALCOMM IncorporatedInventors: Kambiz Samadi, Amin Ansari, Yang Du
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Patent number: 10121743Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.Type: GrantFiled: March 29, 2017Date of Patent: November 6, 2018Assignee: QUALCOMM IncorporatedInventors: Pratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du
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Publication number: 20180286800Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.Type: ApplicationFiled: March 29, 2017Publication date: October 4, 2018Inventors: Pratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du
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Publication number: 20180260360Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC.Type: ApplicationFiled: March 7, 2017Publication date: September 13, 2018Inventors: Kambiz Samadi, Amin Ansari, Yang Du
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Patent number: 9929733Abstract: A 3D integrated circuit reduces delay when a signal traverses logical blocks of the integrated circuit. In one instance, the 3D integrated circuit has a first tier and a second tier including one or more first and second logical blocks, respectively. The first logical block(s) include a first primary output logic gate, a first primary input logic gate, a first primary input pin and a first primary output pin. The first primary output pin lies within a perimeter defined by a total area occupied by logic gates of the first logical block(s). The second logical block(s) include a second primary output logic gate, a second primary input logic gate, a second primary input pin and a second primary output pin. The second primary input pin is coupled to the first primary output pin.Type: GrantFiled: February 21, 2017Date of Patent: March 27, 2018Assignee: QUALCOMM IncorporatedInventors: Pratyush Kamal, Kambiz Samadi, Jing Xie, Yang Du
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Patent number: 9754923Abstract: Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs) are disclosed. Exemplary aspects of the present disclosure contemplate consolidating power gating circuits or cells into a single tier within a 3DIC. Still further, the power gating circuits are consolidated in a tier closest to a voltage source. This closest tier may include a backside metal layer that allows a distance between the voltage source and the power gating circuits to be minimized. By minimizing the distance between the voltage source and the power gating circuits, power loss from routing elements therebetween is minimized. Further, by consolidating the power gating circuits in a single tier, routing distances between the power gating circuits and downstream elements may be minimized and power loss from those routing elements are minimized. Other advantages are likewise realized by placement of the power gating circuits according to exemplary aspects of the present disclosure.Type: GrantFiled: May 9, 2016Date of Patent: September 5, 2017Assignee: QUALCOMM IncorporatedInventors: Jing Xie, Kambiz Samadi, Pratyush Kamal, Yang Du, Javid Jaffari
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Patent number: 9741691Abstract: Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.Type: GrantFiled: April 29, 2015Date of Patent: August 22, 2017Assignee: QUALCOMM IncorporatedInventors: Sung Kyu Lim, Kambiz Samadi, Yang Du
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Patent number: 9626311Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.Type: GrantFiled: January 22, 2015Date of Patent: April 18, 2017Assignee: QUALCOMM IncorporatedInventors: Sung Kyu Lim, Karamvir Singh Chatha, Yang Du, Kambiz Samadi
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Patent number: 9629233Abstract: Methods and apparatus for implementing a synthetic jet to cool a device are provided. Examples of the techniques keep a device case cool enough to be hand-held, while allowing a higher temperature of a circuit component located in the case, to maximize circuit performance. In an example, provided is a mobile device including a synthetic jet configured to transfer heat within the mobile device. The synthetic jet can be embedded in a circuit board inside the mobile device such that the circuit board defines at least a portion of a chamber of the synthetic jet and defines an orifice of the synthetic jet. The device case can define at least one fluid channel inside the mobile device. Also, the circuit board can define a synthetic jet outlet configured to direct a fluid at the at least one fluid channel. Also provided are methods for controlling a synthetic jet.Type: GrantFiled: June 8, 2015Date of Patent: April 18, 2017Assignee: QUALCOMM IncorporatedInventors: Mehdi Saeidi, Arpit Mittal, Emil Rahim, Rajat Mittal, Kambiz Samadi
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Publication number: 20170092558Abstract: An integrated circuit includes inter-digital transducers in a silicon die, where the inter-digital transducers are driven to excite phonons in the silicon die to modulate its thermal conductivity. The thermal conductivity may be increased by exciting acoustic phonons in the silicon die, so that heat dissipation is improved, or the thermal conductivity may be decreased by exciting optical phonons so that heat dissipation is reduced. In conjunction with power management, the thermal conductivity is increased or decreased depending upon the power states of various functional units in the silicon die and depending upon various temperature sensors.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Arpit MITTAL, Mehdi SAEIDI, Kambiz SAMADI
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Patent number: 9569380Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.Type: GrantFiled: January 22, 2015Date of Patent: February 14, 2017Assignee: QUALCOMM IncorporatedInventors: Sung Kyu Lim, Karamvir Singh Chatha, Yang Du, Kambiz Samadi
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Publication number: 20160360606Abstract: Methods and apparatus for implementing a synthetic jet to cool a device are provided. Examples of the techniques keep a device case cool enough to be hand-held, while allowing a higher temperature of a circuit component located in the case, to maximize circuit performance. In an example, provided is a mobile device including a synthetic jet configured to transfer heat within the mobile device. The synthetic jet can be embedded in a circuit board inside the mobile device such that the circuit board defines at least a portion of a chamber of the synthetic jet and defines an orifice of the synthetic jet. The device case can define at least one fluid channel inside the mobile device. Also, the circuit board can define a synthetic jet outlet configured to direct a fluid at the at least one fluid channel. Also provided are methods for controlling a synthetic jet.Type: ApplicationFiled: June 8, 2015Publication date: December 8, 2016Inventors: Mehdi SAEIDI, Arpit MITTAL, Emil RAHIM, Rajat MITTAL, Kambiz SAMADI
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Patent number: 9508615Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.Type: GrantFiled: February 9, 2015Date of Patent: November 29, 2016Assignee: QUALCOMM IncorporatedInventors: Sung Kyu Lim, Kambiz Samadi, Pratyush Kamal, Yang Du