Patents by Inventor Kameran Azadet

Kameran Azadet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor chip providing on-chip self-testing of an ana-log-to-digital converter implemented in the semiconductor chip
    Patent number: 11962320
    Abstract: A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 16, 2024
    Assignee: Intel Corporation
    Inventors: Kameran Azadet, Martin Clara, Daniel Gruber, Albert Molina, Hundo Shin
  • Wireless communication technology, apparatuses, and methods
    Patent number: 11955732
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Digital-to-analog converter, data processing system, base station, and mobile device
    Patent number: 11901908
    Abstract: A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Daniel Gruber, Kameran Azadet, Yu-Shan Wang, Hundo Shin, Martin Clara
  • CREST FACTOR REDUCTION CANCELLATION PULSE HAVING A REDUCED LENGTH
    Publication number: 20240007337
    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) technique that utilizes a cancellation pulse signal having a reduced length. The CFR technique may be applied to a signal to be transmitted, which may comprise a composite signal having one or more carrier signals. Each carrier signal of the composite signal may be filtered via a respective channel filter and then recombined to form the signal to be transmitted, on which the CFR operations are then applied. The length of the cancellation pulse signal is less than the number of taps of the channel filter with the largest number of taps. This reduction in cancellation pulse signal length significantly reduces the processing power required to perform the CFR operations while maintaining regulatory emissions compliance.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Sunitha Motipalli, Kameran Azadet, Albert Molina, Joseph Othmer, Kannan Rajamani
  • CREST FACTOR REDUCTION USING PEAK CANCELLATION WITHOUT PEAK REGROWTH
    Publication number: 20240004957
    Abstract: Techniques are disclosed for the use of Crest Factor Reduction (CFR) algorithm that performs oversampling of an input signal and a cancellation pulse, and detects a set of peak samples in the upsampled input signal that exceed a predetermined threshold value. The peak samples are clustered such that a subset of the oversampled signal peaks are used to compute gain factors for the generation of a scaled truncated upsampled cancellation pulse. Several scaled truncated upsampled cancellation pulses are applied in parallel to perform peak cancellation of the highest peak in each cluster as part of an initial peak cancellation process. Any remaining peaks are canceled by iterative gain factors computation process. A final cancellation pulse is then generated by multiplying a cancellation pulse by the computed gain factors.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Inventors: Sunitha Motipalli, Kameran Azadet, Albert Molina, Joseph Othmer, Kannan Rajamani
  • DATA SYNCHRONIZATION TECHNIQUES FOR A HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE PROCESSING ARRAY ARCHITECTURE
    Publication number: 20240008045
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Kannan Rajamani, Kameran Azadet, Kevin Kinney, Thomas Smith, Zoran Zivkovic
  • CHIP-TO-CHIP INTERFACE OF A MULTI-CHIP MODULE (MCM)
    Publication number: 20230236999
    Abstract: A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.
    Type: Application
    Filed: December 26, 2020
    Publication date: July 27, 2023
    Inventors: Kameran Azadet, Wee Liew, Ramani Tatikola, Edwin Thaller, Patrick Torta, Yu-Shan Wang, Georg Weber, James Yoder
  • HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
    Publication number: 20230205730
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Zoran Zivkovic, Kameran Azadet, Kannan Rajamani, Thomas Smith
  • System and method for calibrating a time-interleaved digital-to-analog converter
    Publication number: 20230208429
    Abstract: A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Albert MOLINA, Kameran AZADET, Martin CLARA, Daniel GRUBER
  • DIGITAL PRE-DISTORTION (DPD) ADAPTATION USING A HYBRID HARDWARE ACCELERATOR AND PROGRAMMABLE ARRAY ARCHITECTURE
    Publication number: 20230205727
    Abstract: Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Zoran Zivkovic, Kameran Azadet, Kannan Rajamani, Thomas Smith
  • SEMICONDUCTOR DEVICES, TRANSCEIVER, BASE STATION AND MOBILE DEVICE
    Publication number: 20230198542
    Abstract: A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.
    Type: Application
    Filed: November 11, 2022
    Publication date: June 22, 2023
    Inventors: Daniel GRUBER, Kameran AZADET, Martin CLARA, Marc Jan Georges TIEBOUT
  • WIRELESS COMMUNICATION SYSTEM AND BASE STATION
    Publication number: 20230198560
    Abstract: A wireless communication system including a phased array comprising a plurality of antennas configured to emit a respective radio wave based on a respective antenna signal. Further, the system includes a plurality of power amplifiers each coupled to one of the plurality of antennas via a feed line and configured to output the antenna signal to the feed line. Also, the system includes a plurality of directional couplers each coupled into one of the feed lines and comprising a third port configured to output a fraction of a power received at a first port coupled to the power amplifier via the feed line, likewise a fourth port configured to output a fraction of a power received at a second port. Additionally, the system includes switching circuitry configured to alternately couple the third port to a first feedback receiver, and to alternately couple the fourth port to a second feedback receiver.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 22, 2023
    Inventors: Marc Jan Georges TIEBOUT, Hazar YUKSEL, Kameran AZADET
  • System and method for calibrating an analog-to-digital converter using a rational sampling frequency calibration digital-to-analog converter
    Publication number: 20230198536
    Abstract: An analog-to-digital conversion system. A clock generator generates a first clock signal at a first frequency. An analog-to-digital converter (ADC) converts an input analog signal to a digital signal. The ADC operates based on the first clock signal at the first frequency. A calibration digital-to-analog converter (DAC) generates an analog reference signal from digital reference data. A fractional rate clock generator generates a second clock signal from the first clock signal. The second clock signal is at a second frequency that is a fractional rate of the first frequency, and the calibration DAC operates at the second frequency. An equalizer processes an output of the ADC to remove a distortion incurred by the ADC and a calibration circuitry generates coefficients for the equalizer based on the digital reference data and the output of the ADC to the analog reference signal.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Inventors: Albert MOLINA, Kameran AZADET, Martin CLARA
  • Method and system for digital pre-distortion using look-up table
    Patent number: 11658672
    Abstract: A digital predistortion system and method for pre-distorting an input to a non-linear system. The digital predistortion system includes a digital predistortion circuit and a memory. The digital predistortion circuit is configured to receive input data and modify the input data using at least one look-up table. The at least one look-up table is addressed by a signed real value of the input data. The memory is configured to store the at least one look-up table. The at least one look-up table is implemented based on a generalized memory polynomial model.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: May 23, 2023
    Assignee: Intel Corporation
    Inventors: Ramon Sanchez, Kameran Azadet
  • WIRELESS COMMUNICATION TECHNOLOGY, APPARATUSES, AND METHODS
    Publication number: 20230145401
    Abstract: Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 11, 2023
    Inventors: Erkan Alpman, Arnaud Lucres Amadjikpe, Omer Asaf, Kameran Azadet, Rotem Banin, Miroslav Baryakh, Anat Bazov, Stefano Brenna, Bryan K. Casper, Anandaroop Chakrabarti, Gregory Chance, Debabani Choudhury, Emanuel Cohen, Claudio Da Silva, Sidharth Dalmia, Saeid Daneshgar Asl, Kaushik Dasgupta, Kunal Datta, Brandon Davis, Ofir Degani, Amr M. Fahim, Amit Freiman, Michael Genossar, Eran Gerson, Eyal Goldberger, Eshel Gordon, Meir Gordon, Josef Hagn, Shinwon Kang, Te Yu Kao, Noam Kogan, Mikko S. Komulainen, Igal Yehuda Kushnir, Saku Lahti, Mikko M. Lampinen, Naftali Landsberg, Wook Bong Lee, Run Levinger, Albert Molina, Resti Montoya Moreno, Tawfiq Musah, Nathan G. Narevsky, Hosein Nikopour, Oner Orhan, Georgios Palaskas, Stefano Pellerano, Ron Pongratz, Ashoke Ravi, Shmuel Ravid, Peter Andrew Sagazio, Eren Sasoglu, Lior Shakedd, Gadi Shor, Baljit Singh, Menashe Soffer, Ra'anan Sover, Shilpa Talwar, Nebil Tanzi, Moshe Teplitsky, Chintan S. Thakkar, Jayprakash Thakur, Avi Tsarfati, Yossi Tsfati, Marian Verhelst, Nir Weisman, Shuhei Yamada, Ana M. Yepes, Duncan Kitchin
  • Segmented digital-to-analog converter with subtractive dither
    Patent number: 11637560
    Abstract: A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and ?1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 25, 2023
    Assignee: Intel Corporation
    Inventors: Martin Clara, Daniel Gruber, Kameran Azadet
  • METHOD AND SYSTEM FOR DIGITAL EQUALIZATION OF A LINEAR OR NON-LINEAR SYSTEM
    Publication number: 20230015514
    Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).
    Type: Application
    Filed: June 25, 2021
    Publication date: January 19, 2023
    Inventors: Albert MOLINA, Martin CLARA, Kameran AZADET
  • Method and apparatus for measuring and cancelling local oscillator feedthrough using an observation receiver
    Publication number: 20220416822
    Abstract: A method and apparatus for cancelling local oscillator feedthrough (LOFT). A transmitter includes a first mixer configured to mix a transmit signal with a first local oscillator signal. An observation receiver receives a fraction of a power of the transmit signal as a feedback signal and processes the feedback signal. The observation receiver includes a second mixer configured to mix the feedback signal with a second local oscillator signal. A LOFT correction estimation circuitry is configured to determine a DC offset to cancel LOFT at the first mixer in the transmitter based on measurements on outputs of the second mixer. An LOFT correction circuitry is configured to add the DC offset to the transmit signal. The LOFT correction estimation circuitry may determine the DC offset based on several measurements obtained by varying the DC offset and a phase shift in the second local oscillator signal in the observation receiver.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Kameran AZADET, Marc Jan Georges TIEBOUT
  • Processing Device, Transmitter, Base Station, Mobile Device, Method and Computer Program
    Publication number: 20220416807
    Abstract: A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Ramon SANCHEZ, Kameran AZADET, Martin CLARA, Daniel GRUBER
  • Method and system for digital correction for a dynamically varying non-linear system
    Publication number: 20220416729
    Abstract: A system and method for digital correction for a dynamically varying non-linear system. The system includes a correction circuitry including at least one look-up table (LUT). The correction circuitry is configured to receive an input signal and modify the input signal to be processed by the non-linear system using at least one LUT to correct non-linearity incurred by the non-linear system. The at least one LUT is addressed by a magnitude or power of the input signal and a dynamically varying parameter associated with the input signal. The dynamically varying parameter may be one of average signal power of the input signal, a differential of the average power of the input signal, a directional beam index, or temperature.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Kameran AZADET, Marc Jan Georges TIEBOUT, Ramon SANCHEZ, Hazar YUKSEL