Patents by Inventor Kamesawara K. Rao

Kamesawara K. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EEPROM utilizing single transistor per cell capable of both byte erase and flash erase
    Patent number: 4949309
    Abstract: An array of floating gate transistors is connected so that some of the floating gate transistors within the array can be erased without affecting the state of other floating gate transistors within the array, or in the alternative, the entire array of floating gate transistors can be erased simultaneously.
    Type: Grant
    Filed: May 11, 1988
    Date of Patent: August 14, 1990
    Assignee: Catalyst Semiconductor, Inc.
    Inventor: Kamesawara K. Rao