Abstract: A method for forming metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. An IC structure is first provided, with the IC structure including a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure in a controlled manner. A photoresist masking layer is then formed on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed.

Abstract: A process for the formation of metal salicide regions and metal salicide exclusion regions in an integrated circuit (IC) that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process, an IC structure is first provided. The IC structure includes a plurality of MOS transistor structures with exposed silicon surfaces, such as source regions, drain regions and polysilicon gates. A metal layer (e.g., cobalt, titanium, tantalum, nickel or molybdenum) is then deposited over the IC structure, followed by the formation of a photoresist masking layer on those MOS transistor structures where metal salicide regions are to be formed. The metal layer from those MOS transistor structures where metal salicide exclusion regions are to be formed is then removed, followed by stripping of the photoresist masking layer from those MOS transistor structures where metal salicide regions are to be formed.

Abstract: A low stress active area silicon island structure with a reduced susceptibility to gate polysilicon layer “wraparound” and stringer formation during subsequent semiconductor manufacturing. The structure includes a semiconductor substrate (e.g. a silicon wafer) with an electrical insulation layer (e.g. a SiO2 layer) thereon. The electrical insulation layer has an active area opening extending from its surface to the surface of the underlying semiconductor substrate. The structure also includes an active area silicon island filling the active area opening. A cross-section of the active area silicon island perpendicular to the surface of the semiconductor substrate has a non-rectangular profile, for example a “wineglass” profile. A process for the formation of a low stress active area silicon island structure includes first providing a semiconductor substrate, followed by forming an electrical insulation layer thereon.

Abstract: A novel apparatus for the deposition of silicon and the formation of silicon films. More specifically, the process provides an aerosol generating technique, wherein silicon powder of optimum particle size is aerosolized, charged, and then electrostatically deposited onto high melting point substrates, which may include semiconducting, insulating, and conducting materials such as silicon, sapphire, and molybdenum, respectively. The powder coated substrates are subsequently heat treated at optimum times and temperatures, resulting in the formation of polycrystalline silicon films.

Abstract: A novel method for the deposition of silicon and the formation of silicon films. More specifically, the process provides an aerosol generating technique, wherein silicon powder of optimum particle size is aerosolized, charged, and then electrostatically deposited onto high melting point substrates, which may include semiconducting, insulating, and conducting materials such as silicon, sapphire, and molybdenum, respectively. The powder coated substrates are subsequently heat treated at optimum times and temperatures, resulting in the formation of polycrystalline silicon films.