Abstract: Techniques and circuits for testing high-speed circuits using slow-speed input signals. Various designs for a “stimulus” generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more input signals. In one design, the generator includes two edge detectors coupled to a latch. Each edge detector receives a respective set of input signals and provides an intermediate signal. The latch receives the two intermediate signals from the two edge detectors and generates the output signal, which has a particular waveform pattern generated based on the active (e.g., leading) transitions in the two sets of input signals provided to the two edge detectors. In another design, the generator includes a ring oscillator that is enabled by one input signal, and further initiated by a pulse on another input signal provided to an input of a latch used to implement the oscillator.

Abstract: Techniques and circuits for testing high-speed circuits using slow-speed input signals. Various designs for a “stimulus” generator are provided, which is capable of generating a high-speed stimulus based on, or in response to, one or more input signals. In one design, the generator includes two edge detectors coupled to a latch. Each edge detector receives a respective set of input signals and provides an intermediate signal. The latch receives the two intermediate signals from the two edge detectors and generates the output signal, which has a particular waveform pattern generated based on the active (e.g., leading) transitions in the two sets of input signals provided to the two edge detectors. In another design, the generator includes a ring oscillator that is enabled by one input signal, and further initiated by a pulse on another input signal provided to an input of a latch used to implement the oscillator.

Abstract: A memory device that includes a row decoder, a set of word line, and one or more word line pull-down drivers. The row decoder includes decoding circuitry and a set of word line drivers. The decoding circuitry is configured to receive address information and generate a set of word line control signals. The word line drivers couple to the decoding circuitry and are responsive to the word line control signals. Each word line driver is configured to provide pull-up drive capability, and can further be configured to provide pull-down drive capability. Each word line couples to at least one word line driver. The word line pull-down driver(s) couples to the word lines, with each word line pull-down driver being configured to provide pull-down drive capability. One or more word line pull-down drivers can be distributed (i.e., uniformly) along the length of each word line. The word lines can also be implemented using a hierarchical word line architecture that includes a set of main word lines (i.e.

Abstract: A method and circuit for accessing data bits in a memory array in a multi-data rate operation. In one architecture, a memory device includes a memory array for storing data values, multiple (N) sensing circuits, multiple (K) control lines, and an I/O pad. One sensing circuit couples to each data value being retrieved from the memory device. The I/O pad operatively couples to the sensing circuits. And each control line couples to at least one sensing circuit and has a clock phase unique from remaining control lines.

Abstract: Methods and circuits for triggering column select line for write operations in a multiple data rate (e.g., a double data rate) operation. A memory device includes a memory array that stores data values, an address logic circuit that generates an address for the memory array, and a column decoder. The column decoder couples to the address logic circuit and the memory array. The column decoder receives either a data strobe input signal (DQS) or a clock signal (CLK), or both, and activates a column select line for the memory array in response to one of the input signal(s).