Abstract: A conductive current collector with modified surfaces can be included as a portion of a bipolar battery assembly. The fabrication process can include deposition or formation of a thin film layer such as metal silicide on a surface of the current collector. Metal silicides can be created by co-sputtering or by annealing after deposition of one or more of a silicon or a metal layer. Additional layers can be provided, such as to facilitate adhesion of an active material to a current collector.

Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.

Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, attaching a prepreg backplane to the interdigitated pattern of base electrodes and emitter electrodes, forming holes in the prepreg backplane which provide access to the first layer of electrically conductive metal, and depositing a second layer of electrically conductive metal on the backside surface of the prepreg backplane forming an electrical interconnect with the first layer of electrically conductive metal through the holes in the prepreg backplane.

Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects as well as Fabrication methods and structures for forming thin film back contact solar cells are described.

Abstract: A reduction in encapsulation height for semiconductor devices is obtained by forming a cavity in a substrate carrying a conductive pattern on an upper surface, and attaching a die to the bottom surface of the substrate, connecting pads on the die exposed within the cavity. Wire bonds connect the connecting pads to the conductive pattern, the wire bonds extending into the cavity.

Abstract: A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion thereof overlies a central region of the laminated substrate. An integrated-circuit die is mounted in the central region of the laminated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the leadframe. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. A solder mask is applied on the second conductive trace pattern so as to form selective solderable areas. Finally, solder balls are attached to the selective solderable areas.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD SiO2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD SiO2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An SiO2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A ball grid array (BGA) package configuration for packaging an integrated-circuit die includes a lead frame having a plurality of inwardly-extending bonding fingers and a centrally-located die-attach pad. The bonding fingers are disposed peripherally surrounding the die-attach pad. An integrated-circuit die is mounted on the die-attach pad. Bonding fingers are interconnected between the bonding pads on the integrated-circuit die and the plurality of bonding fingers. A plastic material is molded over the top of the lead frame and the die while still providing an exposed bottom surface of the bonding fingers on the lead frame. A solder mask is disposed over the bottom of the lead frame so as to form selective solder areas. Solder balls are attached to the selective solder areas.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have an oxygen-plasma oxide formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, the bonding wires are subjected to an oxygen plasma to form an insulating oxide on the bonding wires to prevent short-circuits with adjacent wires. The wires are aluminum or copper with an oxygen-plasma oxide formed thereupon. An oxygen-plasma oxide is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have an oxygen-plasma oxide formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, the bonding wires are subjected to an oxygen plasma to form an insulating oxide on the bonding wires to prevent short-circuits with adjacent wires. The wires are aluminum or copper with an oxygen-plasma oxide formed thereupon. An oxygen-plasma oxide is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A semiconductor integrated circuit package is provided with insulated bonding wires. The semiconductor die is mounted to a base of either a leadframe or a grid-array package. A plurality of bonding wires are bonded between bonding pads on the semiconductor die and bonding fingers at inner ends of package conductors. The bonding wires have a PECVD S.sub.i O.sub.2 layer formed thereupon to thereby provide electrically-insulated bonding wires to prevent short-circuits between adjacent bonding wires. After wire bonding of the bonding wires, an insulating PECVD S.sub.i O.sub.2 layer is formed on the bonding wires to prevent short-circuits with adjacent wires. An S.sub.i O.sub.2 layer is simultaneously formed on a leadframe and is removed from the outer ends of the leads by blasting with a medium.

Abstract: A method for fabricating a chip size package is provided. The method includes the step of forming a laminated substrate which consists of a dielectric layer and a highly conductive layer disposed thereon. Holes are drilled into the dielectric layer. A desired pattern is applied to the conductive layer. A chip structure is formed which consists of a silicon die and an insulating layer disposed thereon. Gold bumps are applied to the top surface of the bonding pads. The laminated substrate is bonded to the chip structure via the holes and gold bumps. A solder mask is applied over the top surface of the conductive layer of the laminated substrate so as to form selective solder areas. Finally, solder balls are attached to the selective solder areas.

Abstract: A high density leaded ball-grid array package for packaging an integrated-circuit die includes a laminated substrate formed of a non-conductive layer sandwiched between first and second conductive trace patterns. A leadframe is directly attached onto the first conductive trace pattern of the laminated substrate by a non-conductive adhesive so that the open portion thereof overlies a central region of the laminated substrate. An integrated-circuit die is mounted in the central region of the laminated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the leadframe. A plastic material is molded over the top surface of the die, bonding fingers and bonding wires. A solder mask is applied on the second conductive trace pattern so as to form selective solderable areas. Finally, solder balls are attached to the selective solderable areas.

Abstract: A ball grid array (BGA) package configuration for packaging an integrated-circuit die includes a lead frame having a plurality of inwardly-extending bonding fingers and a centrally-located die-attach pad. The bonding fingers are disposed peripherally surrounding the die-attach pad. An integrated-circuit die is mounted on the die-attach pad. Bonding fingers are interconnected between the bonding pads on the integrated-circuit die and the plurality of bonding fingers. A plastic material is molded over the top of the lead frame and the die while still providing an exposed bottom surface of the bonding fingers on the lead frame. A solder mask is disposed over the bottom of the lead frame so as to form selective solder areas. Solder balls are attached to the selective solder areas.

Abstract: A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a plurality of inwardly-extending bonding fingers has the bottom sides thereof attached to the top surface of the substrate by a non-conductive adhesive so that an open portion thereof overlies the integrated-circuit die. The plurality of bonding fingers are disposed so as to peripherally surround the integrated-circuit die. A double-sided printed circuit board having first and second conductive layers disposed on its opposite sides is disposed over and bonded to the lead frame. Bonding wires are used to interconnect bonding pads on the integrated-circuit die to the first and second conductive layers. A plastic material is molded around the substrate, die, lead frame, printed circuit board and conductive layers.

Abstract: A high density ball-grid array package for packaging an integrated-circuit die includes a laminated structure formed of a dielectric layer and a high conductive layer disposed thereon. The dielectric layer has a plurality of first drilled holes, and the conductive layer is formed with a desired pattern. An insulated layer is provided with a plurality of second drilled holes. The laminated substrate is bonded to the insulated substrate so that the plurality of first drilled holes are aligned with corresponding ones of the plurality of second drilled holes in order to form selective solderable areas on the bottom side of the package. The laminated structure has an open portion overlying a central region of the insulated substrate on the top side of the package. An integrated-circuit die is mounted in the central region of the insulated substrate. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and bonding fingers formed on the conductive layer of laminated structure.

Abstract: A leadframe ball grid array package for packaging an integrated-circuit die includes a metallic substrate having a central portion and a leadflame having a plurality of inwardly-extending bonding fingers and a centrally-located open portion. The leadframe is directly attached to the metallic substrate by a non-conductive adhesive so that the open portion thereof overlies the central recessed portion of the metallic substrate. An integrated-circuit die is mounted in the central portion of the metallic substrate. The bonding fingers are disposed peripherally surrounding the integrated-circuit die. Bonding wires are interconnected between bonding pads formed on the integrated-circuit die and the plurality of bonding fingers. A solder mask is disposed over the top surface of the leadframe so as to form selective solderable areas. Solder balls are attached to the selective solderable areas. A plastic material or a lid is applied over the top surface of the die, bonding fingers and bonding wires.

Abstract: A multi-layer substrate structure and a method for fabricating the same are provided. Thin metal foils are laminated on the top and bottom sides of a non-conductive layer so as to form a laminated substrate. A plurality of plated-through holes are formed in the laminated substrate and are then filled with an epoxy. The laminated substrate is then patterned and etched. Epoxy layers are disposed on both sides of the laminated substrate. The laminated substrate is formed with a plurality of smaller plated-through holes extending through the epoxy layers and with a cavity to receive an integrated-circuit die. The through holes and the epoxy layers are metallized on both sides of the laminated substrate. The laminated substrate is patterned and etched again. A solder mask is applied on both sides of the laminated substrate so as to form selective wire bondable areas and selective solderable areas. The integrated circuit die is disposed in the center of the cavity and has a plurality of bonding pads.

Abstract: A semiconductor substrate layer is provided which includes a plurality of severed through holes (or metallized half vias) along an edge portion of the substrate layer. The bonding fingers of a leadframe are then formed into a down set (or up set) format and soldered to the substrate at the severed, plated through holes. This technique increases the contact area between the leadframe and the substrate. In addition, the down set (or up set) format of the leadframe bonding fingers decreases the stress built up due to CTE mismatch between the substrate and the leadframe.

Abstract: A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a plurality of inwardly-extending bonding fingers has the bottom sides thereof attached to the top surface of the substrate by a non-conductive adhesive so that an open portion thereof overlies the integrated-circuit die. The plurality of bonding fingers are disposed so as to peripherally surround the integrated-circuit die. A double-sided printed circuit board having first and second conductive layers disposed on its opposite sides is disposed over and bonded to the lead frame. Bonding wires are used to interconnect bonding pads on the integrated-circuit die to the first and second conductive layers. A plastic material is molded around the substrate, die, lead frame, printed circuit board and conductive layers.