Patents by Inventor Kana Ono

Kana Ono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977789
    Abstract: A display screen generation apparatus includes: an acquisition portion acquiring for each of a plurality of print products produced through a plurality of processes, progress of the processes; and a display portion generating a display screen that displays for each of the plurality of print products, the process waiting to be executed, the process being executed, the process already executed, and the process not intended to be executed in a distinguishable manner from each other.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuyuki Minamihara, Kana Ogawa, Toshiaki Kimura, Yoshiki Katsuma, Yuto Fukuchi, Ayako Kobayashi, Satoru Ono, Yuichi Sugiyama
  • Patent number: 7555702
    Abstract: An error correction device, an error correction program and an error correction method can reduce the processing time necessary for the process of correcting errors that involve erasure in a reception word by using a software and hardware properly and effectively. As an error-correcting circuit for correcting errors that do not involve erasure receives a reception word that involves erasure from an RDC, an erasure information holding section holds the erasure information and a syndrome generating section generates a syndrome from the reception word so that a erasure judging section transmits the erasure information and the syndrome to an MPU. In the MPU, an erasure error value computing section and erasure correcting section correct only erasure and store the reception word that does not involve erasure in an RAM. The reception word from the RAM is input again to the error-correcting circuit for correcting errors that do not involve erasure by way of a data bus and a switch.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: June 30, 2009
    Assignee: Fujitsu Limited
    Inventor: Kana Ono
  • Publication number: 20070136646
    Abstract: An error correction device, an error correction program and an error correction method can reduce the processing time necessary for the process of correcting errors that involve erasure in a reception word by using a software and hardware properly and effectively. As an error-correcting circuit 3a for correcting errors that do not involve erasure receives a reception word that involves erasure from an RDC 2, an erasure information holding section 3a1 holds the erasure information and a syndrome generating section 3a2 generates a syndrome from the reception word so that a erasure judging section 3a3 transmits the erasure information and the syndrome to an MPU 4. In the MPU 4, an erasure error value computing section 4a3 and erasure correcting section 4a4 correct only erasure and store the reception word that does not involve erasure in an RAM 3b.
    Type: Application
    Filed: February 10, 2006
    Publication date: June 14, 2007
    Inventor: Kana Ono
  • Patent number: 7191382
    Abstract: When data is read from a disk and stored in volatile memory, check bits are generated and stored in the memory using an algorithm such as cyclical redundancy check (CRC). The CRC algorithm operates on the basis of the bit length in which the data is organized, such as 8 bits. If the data has errors, an error correction code (ECC) algorithm is used to correct the data errors, but the ECC algorithm operates on the basis of symbols having a different bit length, such as 10 bits. To avoid having to re-read the data from the volatile memory to adjust the CRC value, the CRC algorithm is executed on selected mask data developed by the ECC algorithm, the CRC algorithm being executed on the basis of the second bit length to generate a CRC mask. The CRC mask corrects the stored CRC value.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Michael James, Kana Ono
  • Publication number: 20040243885
    Abstract: When data is read from a disk and stored in a volatile staging memory, check bits are generated and stored in the memory using an algorithm such as cyclical redundancy check (CRC). The CRC algorithm operates on the basis of the bit length in which the data is organized, such as 8 bits or 1 byte. If the data has errors, another algorithm such as an error correction code (ECC) algorithm is used to correct the data errors, but the ECC algorithm operates on the basis of symbols having a different bit length, such as 10 bits. To avoid having to re-read the data from the volatile memory to adjust the CRC value, the CRC algorithm is executed on selected mask data developed by the ECC algorithm, the CRC algorithm being executed on the basis of the second bit length to generate a CRC mask. The CRC mask corrects the stored CRC value through an XOR calculation, so that the resulting CRC value reflects the corrected errors.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 2, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Michael James, Kana Ono