Patents by Inventor Kanakasabapathi Subramanian

Kanakasabapathi Subramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7339244
    Abstract: A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are oxidized in one embodiment to form a silicon wire corresponding to each ripple. The oxide is removed in a further embodiment to form structures ranging from micro sharp tips to photonic arrays of wires. Fluidic channels are formed by oxidizing adjacent rippled sidewalls. The same mask is also used to form other structures for MEMS devices.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: March 4, 2008
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Kanakasabapathi Subramanian, Noel C. MacDonald
  • Patent number: 7332835
    Abstract: MEMS-based switching module, as may be electrically connected to other such modules in a series circuit, to achieve a desired voltage rating is provided. A switching array may be made up of a plurality of such switching modules (e.g., used as building blocks of the switching array) with circuitry configured so that any number of modules can be connected in series to achieve the desired voltage rating (e.g., voltage scalability).
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: February 19, 2008
    Assignee: General Electric Company
    Inventors: Joshua Isaac Wright, Kanakasabapathi Subramanian, William James Premerlani, John Norton Park, Kuna Venkat Satya Rama Kishore
  • Patent number: 7305889
    Abstract: According to some embodiments, an apparatus includes a substrate that defines a plane. The apparatus also includes a first conducting plate that is substantially normal to the substrate and a second conducting plate that is (i) substantially normal to the substrate and (ii) deformable in response to a pressure.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 11, 2007
    Assignee: General Electric Company
    Inventors: Jeffrey Fortin, Kuna Kishore, Kanakasabapathi Subramanian
  • Patent number: 7296476
    Abstract: According to some embodiments, an apparatus includes a substrate that defines a plane. The apparatus also includes a first conducting plate that is substantially normal to the substrate and a second conducting plate that is (i) substantially normal to the substrate and (ii) deformable in response to a pressure.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: November 20, 2007
    Assignee: General Electric Company
    Inventors: Jeffrey Fortin, Kuna Kishore, Kanakasabapathi Subramanian
  • Publication number: 20070139831
    Abstract: A system is presented. The system includes a micro-electromechanical system switch. Further, the system includes a balanced diode bridge configured to suppress arc formation between contacts of the micro-electromechanical system switch. A pulse circuit is coupled to the balanced diode bridge to form a pulse signal in response to a fault condition. An energy-absorbing circuitry is coupled in a parallel circuit with the pulse circuit and is adapted to absorb electrical energy resulting from the fault condition without affecting a pulse signal formation by the pulse circuit.
    Type: Application
    Filed: November 28, 2006
    Publication date: June 21, 2007
    Inventors: Joshua Isaac Wright, Kanakasabapathi Subramanian, William James Premerlani, John Norton Park
  • Publication number: 20070141808
    Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.
    Type: Application
    Filed: February 22, 2007
    Publication date: June 21, 2007
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jeffrey Fortin, Guanghua Wu, Kanakasabapathi Subramanian
  • Publication number: 20070139829
    Abstract: A system is presented. The system includes a first micro-electromechanical system switch. Further, the system includes arc suppression circuitry coupled to the first micro-electromechanical system switch, wherein the arc suppression circuitry comprises a balanced diode bridge and is configured to facilitate suppression of an arc formation between contacts of the first micro-electromechanical system switch.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: Stephen Arthur, Kanakasabapathi Subramanian, William Premerlani, John Park, Ajit Achuthan, Wensen Wang, Joshua Wright, Kristina Korosi, Somashekhar Basavaraj
  • Publication number: 20070138584
    Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.
    Type: Application
    Filed: February 22, 2007
    Publication date: June 21, 2007
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Jeffrey Fortin, George Wu, Kanakasabapathi Subramanian
  • Publication number: 20070139830
    Abstract: A system is presented. The system includes detection circuitry configured to detect occurrence of a zero crossing of an alternating source voltage or an alternating load current. The system also includes switching circuitry coupled to the detection circuitry and comprising a micro-electromechanical system switch. Additionally, the system includes control circuitry coupled to the detection circuitry and the switching circuitry and configured to perform arc-less switching of the micro-electromechanical system switch responsive to a detected zero crossing of an alternating source voltage or alternating load current.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 21, 2007
    Inventors: William Premerlani, Kanakasabapathi Subramanian, Christopher Keimel, John Park, Ajit Achuthan, Wensen Wang, Joshua Wright, Kristina Korosi, Somashekhar Basavaraj
  • Publication number: 20070139145
    Abstract: A micro-electromechanical system (MEMS) switch array for power switching includes an input node, an output node, and a plurality of MEMS switches, wherein the input node and the output node are independently in electrical communication with a portion of the plurality of MEMS switches, and wherein a failure of any one of the plurality of MEMS switches does not render ineffective another MEMS switch within the MEMS switch array.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 21, 2007
    Inventors: Kanakasabapathi Subramanian, William Premerlani, Ahmed Elasser, Stephen Arthur, Somashekhar Basavaraj
  • Publication number: 20070125745
    Abstract: A method of manufacturing an ignition device is provided. The method includes patterning a plurality of resistors on a membrane to form heating elements and thermally isolating the heating elements from an external environment via a cavity disposed adjacent to the heating elements.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Kanakasabapathi Subramanian, Richard Saia, Aaron Knobloch, David Najewicz, Nicholas Okruch
  • Publication number: 20070128563
    Abstract: An ignition device for a gas appliance is provided. The ignition device includes a membrane and a plurality of heating elements embedded in the membrane, wherein the heating elements comprise a plurality of patterned resistors and wherein the plurality of heating elements are configured to heat a surface on application of voltage through the heating elements. The ignition device also includes a cavity disposed adjacent to the heating elements and configured to provide thermal isolation of the heating elements.
    Type: Application
    Filed: December 7, 2005
    Publication date: June 7, 2007
    Inventors: Kanakasabapathi Subramanian, Richard Saia, Aaron Knobloch, Nicholas Okruch, David Najewicz
  • Publication number: 20070074578
    Abstract: A differential pressure sensing system is provided. The sensing system includes a membrane layer having a channel extending diametrically therein, and including one or more cavities provided radially outbound of the channel and at least one resonant beam disposed in the channel and configured to oscillate at a desired frequency. The system further includes sensing circuitry configured to detect oscillation of the at least one resonant beam indicative of deformation in the membrane layer.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Kanakasabapathi Subramanian, Kuna Kishore, Parag Thakre, Russell Craddock, Peter Kinnell, John Greenwood
  • Patent number: 7181972
    Abstract: A sensor, in accordance with aspects of the present technique, is provided. The sensor comprises a membrane formed of gallium nitride. The membrane is disposed on a substrate, which is wet-etched to form a closed cavity. The membrane exhibits both a capacitive response and a piezo-response to an external stimulus. The sensor further includes a circuit for measuring at least one of the capacitive response or the piezo-response. In certain aspects, the sensor may be operable to measure external stimuli, such as, pressure, force and mechanical vibration.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: February 27, 2007
    Assignee: General Electric Company
    Inventors: Samhita Dasgupta, Jeffrey Bernard Fortin, Steven Francis LeBoeuf, Vinayak Tilak, Chayan Mitra, Kanakasabapathi Subramanian, Steven Alfred Tysoe
  • Publication number: 20070000330
    Abstract: A pressure sensor is provided. The pressure sensor includes a multi-layer laminate comprising a substrate and a semiconductor layer, wherein the substrate comprises single crystal or quasi-single crystal aluminum oxide, and a portion of the substrate that is spaced from a peripheral edge is wet etched to form an inwardly facing sidewall that defines a volume; and a substrate to which the multi-layer laminate is secured. The volume is an enclosed volume further defined by a substrate surface.
    Type: Application
    Filed: September 6, 2006
    Publication date: January 4, 2007
    Applicant: General Electric Company
    Inventors: Steven Tysoe, Mark D'Evelyn, Charles Becker, Abasifreke Ebong, Stephen Arthur, Steven LeBoeuf, Robert Wojnarowski, Samhita Dasgupta, Vinayak Tilak, Kanakasabapathi Subramanian, Jeffrey Fortin
  • Publication number: 20060289386
    Abstract: An etchant including a halogenated salt, such as Cryolite (Na3AlF6) or potassium tetrafluoro borate (KBF4), is provided. The salt may be present in the etchant in an amount sufficient to etch a substrate and may have a melt temperature of greater than about 200 degrees Celsius. A method of wet etching may include contacting an etchant to at least one surface of a support layer of a multi-layer laminate, wherein the support layer may include aluminum oxide; or contacting an etchant to at least one surface of a support layer of a multi-layer laminate, wherein the etchant may include Cryolite (Na3AlF6), potassium tetrafluoro borate (KBF4), or both; and etching at least a portion of the support layer. The method may provide a laminate produced by growing a crystal onto an aluminum oxide support layer, and chemically removing at least a portion of the support layer by wet etch. An electronic device, optical device or combined device including the laminate is provided.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Steven Tysoe, Steven LeBoeuf, Mark D'Evelyn, Venkat Venkataramani, Vinayak Tilak, Jeffrey Fortin, Charles Becker, Stephen Arthur, Samhita Dasgupta, Kanakasabapathi Subramanian, Robert Wojnarowski, Abasifreke Ebong
  • Publication number: 20060274470
    Abstract: A device for controlling the flow of electric current is provided. The device comprises a first conductor; a second conductor switchably coupled to the first conductor to alternate between an electrically connected state with the first conductor and an electrically disconnected state with the first conductor. At least one conductor further comprises an electrical contact, the electrical contact comprising a solid matrix comprising a plurality of pores; and a filler material disposed within at least a portion of the plurality of pores. The filler material has a melting point of less than about 575K. A method to make an electrical contact is provided. The method includes the steps of: providing a substrate; providing a plurality of pores on the substrate; and disposing a filler material within at least a portion of the plurality of pores. The filler material has a melting point of less than about 575K.
    Type: Application
    Filed: July 5, 2006
    Publication date: December 7, 2006
    Inventors: Duraiswamy Srinivasan, Reed Corderman, Christopher Keimel, Somasundaram Gunasekaran, Sudhakar Reddy, Arun Gowda, Kanakasabapathi Subramanian
  • Publication number: 20060260411
    Abstract: According to some embodiments, an apparatus includes a substrate that defines a plane. The apparatus also includes a first conducting plate that is substantially normal to the substrate and a second conducting plate that is (i) substantially normal to the substrate and (ii) deformable in response to a pressure.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Jeffrey Fortin, Kuna Kishore, Kanakasabapathi Subramanian
  • Publication number: 20060260410
    Abstract: According to some embodiments, an apparatus includes a substrate that defines a plane. The apparatus also includes a first conducting plate that is substantially normal to the substrate and a second conducting plate that is (i) substantially normal to the substrate and (ii) deformable in response to a pressure.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Jeffrey Fortin, Kuna Kishore, Kanakasabapathi Subramanian
  • Publication number: 20060249841
    Abstract: A process cycles between etching and passivating chemistries to create rough sidewalls that are converted into small structures. In one embodiment, a mask is used to define lines in a single crystal silicon wafer. The process creates ripples on sidewalls of the lines corresponding to the cycles. The lines are oxidized in one embodiment to form a silicon wire corresponding to each ripple. The oxide is removed in a further embodiment to form structures ranging from micro sharp tips to photonic arrays of wires. Fluidic channels are formed by oxidizing adjacent rippled sidewalls. The same mask is also used to form other structures for MEMS devices.
    Type: Application
    Filed: January 26, 2006
    Publication date: November 9, 2006
    Inventors: Kanakasabapathi Subramanian, Noel MacDonald