Patents by Inventor Kaname Yamasaki
Kaname Yamasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8400853Abstract: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.Type: GrantFiled: May 12, 2010Date of Patent: March 19, 2013Assignee: Renesas Electronics CorporationInventors: Chizu Matsumoto, Kaname Yamasaki, Michinobu Nakao, Yoshikazu Saitou
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Publication number: 20100290299Abstract: A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.Type: ApplicationFiled: May 12, 2010Publication date: November 18, 2010Inventors: Chizu MATSUMOTO, Kaname Yamasaki, Michinobu Nakao, Yoshikazu Saitou
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Patent number: 7774667Abstract: The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.Type: GrantFiled: March 24, 2008Date of Patent: August 10, 2010Assignee: Renesas Technology Corp.Inventors: Tatsuya Saito, Kaname Yamasaki, Iwao Suzuki, Takeshi Bingo, Keiichi Horie
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Publication number: 20090063913Abstract: Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. Since the self-test part has plural test sequencers corresponding to plural test modes, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs.Type: ApplicationFiled: March 11, 2008Publication date: March 5, 2009Inventors: Kaname Yamasaki, Yoshio Takamine
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Publication number: 20080263414Abstract: The test design cost of a circuit capable of accessing an external memory is reduced. There is included a built-in self-test circuit for use in testing an external memory separately from a memory controller for performing memory control in response to an access request to the external memory capable of being coupled to a memory interface, and a TAP controller is used to control the built-in self-test circuit and referring to a test result. There is adopted a multiplexer for switchably selecting the memory controller or the built-in self-test circuit as a circuit for coupling to the memory interface in accordance with control information externally inputted through the TAP controller. The built-in self-test circuit programmably generates and outputs a pattern for a memory test in accordance with an instruction inputted through the TAP controller, and compares data read from the external memory with an expected value.Type: ApplicationFiled: March 24, 2008Publication date: October 23, 2008Inventors: Tatsuya Saito, Kaname Yamasaki, Iwao Suzuki, Takeshi Bingo, Keiichi Horie
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Patent number: 7366965Abstract: Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.Type: GrantFiled: July 16, 2004Date of Patent: April 29, 2008Assignee: Renesas Technology, Corp.Inventors: Kaname Yamasaki, Yoshio Takamine
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Publication number: 20060184848Abstract: The logic integrated circuit comprises a logic circuit having the predetermined logic functions, a read/write memory circuit, a test circuit for testing whether fail bit is included in the memory circuit or not, and a boundary latch circuit formed of a plurality of flip-flop circuits which are capable of latching signals between said logic circuit and said memory circuit and also forming a shift register. Moreover, the logic integrated circuit is further provided with a fail relief information generating circuit for storing test result to the boundary latch circuit during execution of the test with the test circuit and generating the fail relief information for relieving fail of said memory circuit based on the stored test result. The test circuit mounted on the logic integrated circuit can generate the information for relieving fail bit in parallel with the test of a built-in memory circuit and can also output the same information to external side and relieve the RAM within a chip.Type: ApplicationFiled: January 20, 2006Publication date: August 17, 2006Inventors: Mitsuo Serizawa, Kaname Yamasaki, Masafumi Yamamoto, Kazuo Kato
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Patent number: 6998878Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.Type: GrantFiled: January 12, 2004Date of Patent: February 14, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Publication number: 20050047260Abstract: Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.Type: ApplicationFiled: July 16, 2004Publication date: March 3, 2005Inventors: Kaname Yamasaki, Yoshio Takamine
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Patent number: 6807115Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: GrantFiled: February 10, 2003Date of Patent: October 19, 2004Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
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Publication number: 20040169527Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.Type: ApplicationFiled: January 12, 2004Publication date: September 2, 2004Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Patent number: 6677782Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.Type: GrantFiled: April 24, 2001Date of Patent: January 13, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Patent number: 6617610Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: GrantFiled: December 13, 2001Date of Patent: September 9, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
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Publication number: 20030123309Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: ApplicationFiled: February 10, 2003Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
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Publication number: 20020196053Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.Type: ApplicationFiled: August 29, 2002Publication date: December 26, 2002Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Patent number: 6476644Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.Type: GrantFiled: November 30, 2000Date of Patent: November 5, 2002Assignee: Hitachi, Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Noboru Masuda, Kenji Kaneko, Makoto Hanawa, Takeshi Kusunoki
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Patent number: 6438050Abstract: A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.Type: GrantFiled: January 8, 2002Date of Patent: August 20, 2002Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Fumihiko Arakawa
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Publication number: 20020098602Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: ApplicationFiled: December 13, 2001Publication date: July 25, 2002Applicant: Hitachi, Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
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Publication number: 20020057612Abstract: A transmission circuit for transmitting a data signal between circuit units through a signal wire. The data signal is transmitted for precharging the signal wire to high potential during a precharge period and discharging it to low potential according to data transmitted during an evaluation period or keeping the signal wire as it is. Latch type Source-Coupled-Logic is configured so that a first node and a second node used as an output terminal to the next stage are respectively charged together to high potential during the precharge period. The second node is discharged according to a potential at the first node during the evaluation period, and the first node is discharged according to a potential on the signal wire. Thus, the operation of discharging the signal wire by the driver circuit can be sped up.Type: ApplicationFiled: January 8, 2002Publication date: May 16, 2002Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Fumihiko Arakawa
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Patent number: 6369617Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.Type: GrantFiled: November 10, 1999Date of Patent: April 9, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa