Patents by Inventor Kandis Mae Knoblauch

Kandis Mae Knoblauch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a semiconductor component
    Patent number: 6726826
    Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: April 27, 2004
    Assignee: Motorola, Inc.
    Inventors: Timothy Lee Johnson, Joseph English, David Austin, George F. Carney, Kandis Mae Knoblauch, Douglas G. Mitchell
  • Method of manufacturing a semiconductor component and plating tool therefor
    Publication number: 20020040853
    Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.
    Type: Application
    Filed: November 5, 2001
    Publication date: April 11, 2002
    Inventors: Timothy Lee Johnson, Joseph English, David Austin, George F. Carney, Kandis Mae Knoblauch, Douglas G. Mitchell
  • Method of manufacturing a semiconductor component and plating tool therefor
    Patent number: 6361675
    Abstract: A method of manufacturing a semiconductor component includes depositing a first electrically conductive layer (675) over a substrate (270), forming a patterned plating mask (673) over the first electrically conductive layer, coupling a first plating electrode (250) to the first electrically conductive layer without puncturing the plating mask, and plating a second electrically conductive layer onto portions of the first electrically conductive layer. A plating tool for the manufacturing method includes an inner weir (220) located within an outer weir (210), an elastic member (230) over a rim (211) of the outer weir, a pressure ring (240) located over the rim of the outer weir and the elastic member, and a plurality of cathode contacts (250, 251, 252, 253) located between the pressure ring and the outer weir. The substrate is positioned between the elastic member and the pressure ring.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: March 26, 2002
    Assignee: Motorola, Inc.
    Inventors: Timothy Lee Johnson, Joseph English, David Austin, George F. Carney, Kandis Mae Knoblauch, Douglas G. Mitchell