Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region on a substrate, and a 2nd source/drain region on the 1st source/drain region; and a 1st source/drain contact structure on the 1st source/drain region, and a 2nd source/drain contact structure on the 2nd source/drain region, wherein the 2nd source/drain region is isolated from the 1st source/drain region through an interlayer structure, and wherein a spacer is formed at an upper portion of a sidewall of the 2nd source/drain contact structure, between the 1st source/drain contact structure and the 2nd source/drain contact structure.

Abstract: A cell architecture including at least one semiconductor device cell is provided.

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the Pt fin structures.

Abstract: Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and a first gate structure on the first channel region. A lower surface of the first source/drain region may be higher than a lower surface of the first gate structure relative to the substrate.

Abstract: Provided is field-effect transistor structure including: a channel structure; a source/drain region and a 2nd source/drain region connected to each other through the channel structure; a 1st contact plug, on a top surface of the 1st source/drain region, connected to a voltage source or 1st circuit element through a back-end-of-line (BEOL) structure; and a 2nd contact plug, on a bottom surface of the 2nd source/drain region, connected to the 1st voltage source, through a backside power rail, or another circuit element, wherein the 1st source/drain region and the 2nd source/drain region have a substantially same height.

Abstract: Integrated circuit devices may include a first upper channel region on a substrate, a first lower channel region between the substrate and the first upper channel region, a first intergate insulator that is between the first lower channel region and the first upper channel region and includes a lower portion and an upper portion, an upper gate electrode, and a lower gate electrode between the substrate and the upper gate electrode. The first upper channel region and the upper portion of the first intergate insulator may be in the upper gate electrode. The first lower channel region and the lower portion of the first intergate insulator are in the lower gate electrode.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower insulating structure, a transistor on the lower insulating structure, the transistor including a source/drain region, a power rail structure in the lower insulating structure, and a power contact structure that is on the power rail structure and electrically connects the source/drain region to the power rail structure. The power contact structure may include a lower portion that is in the power rail structure.

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a sacrificial layer in a preliminary substrate by adding an element into the preliminary substrate, forming a transistor structure on the preliminary substrate, the transistor structure including a source/drain region, replacing the sacrificial layer with a power contact that comprises an upper surface contacting the source/drain region, and forming a power rail that contacts a lower surface of the power contact.

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Abstract: An integrated circuit device may comprise an upper transistor that is on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor that is between the substrate and the upper transistor. The lower transistor may comprise a lower channel region. The integrated circuit device may further include an integrated insulator that is between the lower channel region and the upper channel region. The integrated insulator may comprise an outer layer and an inner layer in the outer layer, wherein the inner layer and the outer layer comprise different materials.

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including a channel region and a source/drain region contacting the channel region, a power rail that is configured be electrically connected to a power source and is spaced apart from the source/drain region in a first direction, and a power contact that is between the source/drain region and the power rail and contacts both the source/drain region and the power rail. The channel region may overlap the power contact in the first direction.

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.

Abstract: Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.

Abstract: Provided is a multi-stack nanosheet structure that includes: at least a first nanosheet structure and at least a second nanosheet structure, above the substrate, separated from each other, wherein the first nanosheet structure and second nanosheet structure are adjacent to each other; a channel structure comprising a first portion on the first nanosheet structure, a second portion on the second nanosheet structure, and a third portion on the substrate between the first and second portions, wherein the first portion, the second portion and the third portion form a single continuous structure; a gate structure between the first and second portions on the third portion of the channel structure, wherein the gate structure comprises a gate dielectric layer comprising oxide; and at least a first source/drain region on the first nanosheet structure, and at least a second source/drain region on the second nanosheet structure, wherein the first source/drain region and the second source/drain region include an n-type o