Patents by Inventor Kang-Lung Wang
Kang-Lung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190108879Abstract: A sensing circuit includes a first sensing terminal, a second sensing terminal, a second grounding terminal, and a second grounding terminal. The first sensing terminal is connected to a source electrode of a transistor of a memory macro through a bit line. The second sensing terminal is electrically connected to a drain electrode of the transistor of the memory marco through a resistive memory device to a source line, and is not continuously connected to the grounding voltage. The first grounding terminal is used as a reference voltage of a voltage of the first sensing terminal. The second grounding terminal is used as a reference voltage of a voltage of the second sensing terminal. The sensing circuit outputs a sensing signal according to a voltage difference between the first sensing terminal and the second sensing terminal.Type: ApplicationFiled: December 10, 2018Publication date: April 11, 2019Inventors: ALBERT LEE, HOCHUL LEE, KANG-LUNG WANG
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Patent number: 10255976Abstract: A sensing circuit includes a first sensing terminal, a second sensing terminal, a second grounding terminal, and a second grounding terminal. The first sensing terminal is connected to a source electrode of a transistor of a memory macro through a bit line. The second sensing terminal is electrically connected to a drain electrode of the transistor of the memory marco through a resistive memory device to a source line, and is not continuously connected to the grounding voltage. The first grounding terminal is used as a reference voltage of a voltage of the first sensing terminal. The second grounding terminal is used as a reference voltage of a voltage of the second sensing terminal. The sensing circuit outputs a sensing signal according to a voltage difference between the first sensing terminal and the second sensing terminal.Type: GrantFiled: December 10, 2018Date of Patent: April 9, 2019Assignee: INSTON INC.Inventors: Albert Lee, Hochul Lee, Kang-Lung Wang
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Patent number: 10217500Abstract: The present invention relates to an inductive spin-orbit torque device and the method for fabricating the same. The method comprises steps of depositing a two-dimensional thin film using chemical vapor deposition (CVD) and sputtering a ferromagnetic material on the thin film. The crystal structure of the two-dimensional thin film includes at least one lattice plane arranged asymmetrically. The thickness of the two-dimensional thin film includes at least one unit-cell layer. The sum of the at least one unit-cell layer is an odd number. By using the vertical magnetic torque generated by the two-dimensional thin film and the miniaturization in thickness, the device size and the fabrication costs may be reduced.Type: GrantFiled: October 2, 2017Date of Patent: February 26, 2019Assignee: National Applied Research LaboratoriesInventors: Yann-Wen Lan, Qiming Shao, Guoqiang Yu, Kang-Lung Wang, Wen-Kuan Yeh
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Patent number: 10199100Abstract: A sensing circuit includes a first sensing terminal, a second sensing terminal, a second grounding terminal, and a second grounding terminal. The first sensing terminal is connected to a source electrode of a transistor of a memory macro through a bit line. The second sensing terminal is electrically connected to a drain electrode of the transistor of the memory marco through a resistive memory device to a source line, and is not continuously connected to the grounding voltage. The first grounding terminal is used as a reference voltage of a voltage of the first sensing terminal. The second grounding terminal is used as a reference voltage of a voltage of the second sensing terminal. The sensing circuit outputs a sensing signal according to a voltage difference between the first sensing terminal and the second sensing terminal.Type: GrantFiled: September 28, 2017Date of Patent: February 5, 2019Assignee: INSTON INC.Inventors: Albert Lee, Hochul Lee, Kang-Lung Wang
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Patent number: 9972400Abstract: The present disclosure provides a calibration method for a nonvolatile memory device having a plurality of unit cells, each of the unit cells corresponding to a word line and a bit line of the nonvolatile memory device. The calibration method includes: calibrating a word signal pulse of each of the word lines with a first calibration value corresponding to the word line; calibrating a bit signal pulse of each of the bit lines with a second calibration value corresponding to the bit line; and calibrating each of the unit cells according to the word line and the bit line corresponding to the unit cell.Type: GrantFiled: August 22, 2017Date of Patent: May 15, 2018Assignee: INSTON INC.Inventors: Albert Lee, Hochul Lee, Kang-Lung Wang
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Patent number: 9166147Abstract: A ferroelectric device includes a first electrode, a second electrode spaced apart from the first electrode, and a ferroelectric element arranged between the first and second electrodes. The ferroelectric element has a plurality of quasistatic strain configurations that are selectable by the application of an electric field and the device has selectable electromechanical displacement by the application of the electric field.Type: GrantFiled: April 27, 2012Date of Patent: October 20, 2015Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Gregory P. Carman, Kang-Lung Wang, Tao Wu, Alexandre Bur, Pedram Khalili Amiri
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Patent number: 8917562Abstract: As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.Type: GrantFiled: November 25, 2013Date of Patent: December 23, 2014Assignee: The Regents of the University of CaliforniaInventors: Kang-Lung Wang, Chih-Kong K. Yang, Dejan Markovic, Fengbo Ren
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Patent number: 8860006Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.Type: GrantFiled: March 25, 2011Date of Patent: October 14, 2014Assignee: The Regents of the University of CaliforniaInventors: Kang-Lung Wang, Ajey Poovannummoottil, Faxian Xiu
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Patent number: 8772853Abstract: A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.Type: GrantFiled: July 12, 2011Date of Patent: July 8, 2014Assignee: The Regents of the University of CaliforniaInventors: Augustin J. Hong, Ji-Young Kim, Kang-Lung Wang
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Patent number: 8766341Abstract: The embodiments disclosed herein relate to growth of magnesium-oxide on a single crystalline substrate of germanium. The embodiments further describes a method of manufacturing and crystalline structure of a FM/MgO/Ge(001) heterostructure. The embodiments further related to method of manufacturing and a crystalline structure for a high-k dielectric//MgO [100](001)//Ge[110](001) heterostructure.Type: GrantFiled: October 15, 2010Date of Patent: July 1, 2014Assignee: The Regents of the University of CaliforniaInventors: Wei Han, Yi Zhou, Kang-Lung Wang, Roland K. Kawakami
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Publication number: 20140153325Abstract: As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1V supply voltage, which is greater than reference designs achieve at 5 ns performance.Type: ApplicationFiled: November 25, 2013Publication date: June 5, 2014Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Kang-Lung Wang, Chih-Kong K. Yang, Dejan Markovic, Fengbo Ren
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Publication number: 20140042574Abstract: A ferroelectric device includes a first electrode, a second electrode spaced apart from the first electrode, and a ferroelectric element arranged between the first and second electrodes. The ferroelectric element has a plurality of quasistatic strain configurations that are selectable by the application of an electric field and the device has selectable electromechanical displacement by the application of the electric field.Type: ApplicationFiled: April 27, 2012Publication date: February 13, 2014Applicant: The Regents of the University of CaliforniaInventors: Gregory P. Carman, Kang-Lung Wang, Tao Wu, Alexandre Bur, Pedram Khalili Amiri
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Publication number: 20130015429Abstract: A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.Type: ApplicationFiled: July 12, 2011Publication date: January 17, 2013Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Augustin J. Hong, Ji-Young Kim, Kang-Lung Wang
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Publication number: 20110233524Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.Type: ApplicationFiled: March 25, 2011Publication date: September 29, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Kang-Lung Wang, Ajey Poovannummoottil Jacob, Faxian Xiu
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Publication number: 20110089415Abstract: The embodiments disclosed herein relate to growth of magnesium-oxide on a single crystalline substrate of germanium. The embodiments further describes a method of manufacturing and crystalline structure of a FM/MgO/Ge(001) heterostructure. The embodiments further related to method of manufacturing and a crystalline structure for a high-k dielectric//MgO [100](001)//Ge[110](001) heterostructure.Type: ApplicationFiled: October 15, 2010Publication date: April 21, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Wei Han, Yi Zhou, Kang-Lung Wang, Roland K. Kawakami
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Publication number: 20090001419Abstract: Provided are non-volatile memory devices that may realize high integration and have high reliability. A plurality of first semiconductor layers are stacked on a substrate. A plurality of second semiconductor layers are interposed between the plurality of first semiconductor layers, respectively, and are recessed from one end of each of the plurality of first semiconductor layers to define a plurality of first trenches between the plurality of first semiconductor layers. A plurality of first storage nodes are provided on surfaces of the second semiconductor layers inside the plurality of first trenches. Devices may include a plurality of first control gate electrodes that are formed on the plurality of first storage nodes to fill the plurality of first trenches.Type: ApplicationFiled: March 27, 2008Publication date: January 1, 2009Inventors: Jeong-hee Han, Ji-young Kim, Kang Lung Wang, Chung-woo Kim, Soo-doo Chae, Chan-jin Park
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Patent number: 4339869Abstract: A low resistance electrical contact is made to a silicon substrate by forming a layer of a refractory metal on the substrate and thereafter applying a dosage of ions through the layer of refractory metal to the substrate to form a layer of a compound of the refractory metal and silicon at the interface of the layer of refractory metal and the silicon substrate.Type: GrantFiled: September 15, 1980Date of Patent: July 20, 1982Assignee: General Electric CompanyInventors: Robert F. Reihl, Kang-Lung Wang