Patents by Inventor Kang Song

Kang Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11994696
    Abstract: Embodiments of the present application disclose a method for manufacturing a naked-eye 3D device and a naked-eye 3D device. The method includes: forming a display module including a plurality of pixel islands; forming a spacer layer on the display module; and forming a micro-lens array on the spacer layer, wherein the spacer layer is formed to have a thickness such that the plurality of pixel islands are located at a focal plane of the micro-lens array. The method further includes: forming an alignment mark between the spacer layer and the display module, wherein the alignment mark is used for, when forming the micro-lens array, aligning each micro-lens in the micro-lens array with one of the plurality of pixel islands.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: May 28, 2024
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Kang Guo, Renquan Gu, Xin Gu, Feng Zhang, Meili Wang, Guangcai Yuan, Xue Dong, Mengya Song, Duohui Li, Qi Yao, Jing Yu
  • Patent number: 11997383
    Abstract: According to an embodiment of the present invention, disclosed is a camera module comprising: a light output unit for outputting an optical signal to an object; a sensor for receiving an optical signal reflected from the object; and a control unit for acquiring distance information about the object by using the phase difference of the received optical signal, wherein the sensor includes a non-extraction area from which the phase different is not extracted and an extraction area from which the phase difference is extracted and the control unit stops timing control for the received optical signal in the non-extraction area.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: May 28, 2024
    Assignee: LG Innotek Co., Ltd.
    Inventors: Seok Hyun Kim, Eun Song Kim, Kang Yeol Park
  • Publication number: 20240167943
    Abstract: A method and a system for determining a supporting structure by combining a stress environment and an underground surrounding rock structure are provided in the disclosure, which relates to the technical field of stability analysis of coal-mine rock mass. The method includes: defining a stress peak position and an in-situ stress position by determining the stress environment; identifying the underground surrounding rock structure, identifying lithology and constructing a three-dimensional model of a rock stratum to analyze damage degree of the rock stratum; pretreating, namely normalizing, the damage degree of the rock stratum at two sides and comparing the damage degree of the rock stratum at a roof and the floor; and identifying the supporting structure and determining supporting effectiveness and a supporting length. The method of the disclosure is different from related art, and ensures that the supporting structure meets mechanical foundation and practical engineering requirements as a whole.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 23, 2024
    Inventors: Zhijie WEN, Zhenqi Song, Yujing Jiang, Shucai Li, Yujun Zuo, Jianping Zuo, Kang Peng, Shankun Zhao
  • Patent number: 11990199
    Abstract: Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: May 21, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Taeksang Song, Saira Samar Malik, Hyunyoo Lee, Chinnakrishnan Ballapuram, Kang-Yong Kim
  • Publication number: 20240162309
    Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region on a substrate, and a 2nd source/drain region on the 1st source/drain region; and a 1st source/drain contact structure on the 1st source/drain region, and a 2nd source/drain contact structure on the 2nd source/drain region, wherein the 2nd source/drain region is isolated from the 1st source/drain region through an interlayer structure, and wherein a spacer is formed at an upper portion of a sidewall of the 2nd source/drain contact structure, between the 1st source/drain contact structure and the 2nd source/drain contact structure.
    Type: Application
    Filed: April 17, 2023
    Publication date: May 16, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung YANG, Myunghoon JUNG, Seungmin SONG, Seungchan YUN, Sejung PARK, Kang-ill SEO
  • Patent number: 11956991
    Abstract: A display panel includes a substrate and a grating disposed on a light-emitting side of the display panel. The grating includes a plurality of protruding portions and a plurality of interval portions, each interval portion is located between two adjacent protruding portions. The plurality of protruding portions are arranged on the substrate along a first direction, and each protruding portion extends along a second direction perpendicular to the first direction. Each protruding portion includes an outer surface and a bottom surface; the outer surface is a smooth curved surface, and the bottom surface is a flat surface. A cross-sectional figure of each protruding portion along a thickness direction of the display panel is a first figure; the first figure includes a curve and a bottom edge, and the first figure is a closed figure formed by the curve and the bottom edge.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 9, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jin Zhao, Fudong Chen, Kang Guo, Xueyuan Zhou, Mengya Song, Yanhui Lu, Duohui Li, Ning Dang
  • Patent number: 11956411
    Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Kang, Young-Jun Song, Dong-Ki Min, Jong-Min You, Jee-Hong Lee, Seok-Jae Kang, Taek-Sun Kim, Joon-Hyuk Im
  • Publication number: 20240094343
    Abstract: A method, device, system, and storage medium for tracking a moving target are provided. The method uses three-dimensional radar observation data to construct a state vector and a motion model of the moving target, thereby to construct a state equation and an observation equation for achieving filtering and tracking within a linear Gaussian framework. The disclosure is also suitable for a moving target in a two-dimensional scene with a distance and an azimuth, and the disclosure use a two-dimensional observation vector to construct a dynamic system to achieving tracking of the moving target. The disclosure can be used in radar systems containing Doppler measurements, and tracking of moving targets can be implemented by performing dimension-expansion processing on observation equations.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 21, 2024
    Inventors: XuanZhi Zhao, Wen Zhang, ZengLi Liu, Kang Liu, HaiYan Quan, Yi Peng, JingMin Tang, YaoLian Song, Zheng Chen
  • Patent number: 11935922
    Abstract: A semiconductor device include: a substrate; a 1st transistor formed above the substrate, the 1st transistor including a 1st channel set of a plurality of 1st nanosheet layers, a 1st gate structure surrounding the 1st nanosheet layers, and 1st and 2nd source/drain regions at both ends of the 1st channel set; and a 2nd transistor formed above the 1st transistor in a vertical direction, the 2nd transistor including a 2nd channel set of a plurality of 2nd nanosheet layers, a 2nd gate structure surrounding the 2nd nanosheet layers, and 3rd and 4th source/drain regions at both ends of the 2nd channel set, wherein the 1st channel set has a greater width than the 2nd channel set, wherein a number of the 1st nanosheet layers is smaller than a number of the 2nd nanosheet layers, and wherein a sum of effective channel widths of the 1st nanosheet layers is substantially equal to a sum of effective channel width of the 2nd nanosheet layers.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byounghak Hong, Seunghyun Song, Kang Ill Seo, Hwichan Jun, Inchan Hwang
  • Publication number: 20240086231
    Abstract: This application provides a task migration system and method. The system includes a first terminal and a second terminal. The second terminal runs a first application. The first terminal opens a recent task interface after receiving a user operation, where the recent task interface includes an identifier of the second terminal; after receiving a user operation performed on the identifier of the second terminal, displays, in the recent task interface, at least one task card corresponding to an application run by the second terminal in the background; and after receiving a user operation performed on a first task card corresponding to the first application, runs the first application, and displays a first user interface of the first application.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Kang Chen, Yuhang Song, Hao Huang, Wenjie Huang, Can Jia, Jianhua Zhu, Mingxiang Zhang, Chao Cao, Yanan Zhang, Hongjun Wang, Zhiyan Yang, Chao Xu
  • Publication number: 20240072048
    Abstract: An integrated circuit device may comprise an upper transistor that is on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor that is between the substrate and the upper transistor. The lower transistor may comprise a lower channel region. The integrated circuit device may further include an integrated insulator that is between the lower channel region and the upper channel region. The integrated insulator may comprise an outer layer and an inner layer in the outer layer, wherein the inner layer and the outer layer comprise different materials.
    Type: Application
    Filed: March 16, 2023
    Publication date: February 29, 2024
    Inventors: Seungchan Yun, Seungmin Song, Myunghoon Jung, Keumseok Park, Kang-ill Seo
  • Publication number: 20240066618
    Abstract: A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Applicant: Yield Engineering Systems, Inc.
    Inventors: Lei Jing, M Ziaul Karim, Kenneth Sautter, Kang Song
  • Publication number: 20240072060
    Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 29, 2024
    Inventors: BYOUNGHAK HONG, SEUNGHYUN SONG, KI-IL KIM, GUNHO JO, KANG-ILL SEO
  • Patent number: 11915513
    Abstract: Provided are an apparatus for performing leveling of a person image and an operating method thereof. The method includes: receiving an original person image; selecting an arbitrary latent vector in a latent space; generating a virtual person image based on the latent vector; optimizing the latent vector such that identity similarity between the original person image and the virtual person image increases; manipulating the optimized latent vector; and generating a levelled person image corresponding to the original person image, by using the manipulated latent vector.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 27, 2024
    Assignees: NCSOFT CORPORATION, INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seoungyoon Kang, Min Jae Kim, Moo Kyung Song, Hyunjung Shim, Gun Hee Lee
  • Patent number: 11850672
    Abstract: A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: YIELD ENGINEERING SYSTEMS, INC.
    Inventors: Lei Jing, M Ziaul Karim, Kenneth Sautter, Kang Song
  • Publication number: 20230348912
    Abstract: The present invention relates to a double-stranded oligonucleotide capable of inhibiting amphiregulin expression in a very specific and highly efficient manner, preferably a double-stranded oligonucleotide comprising a sequence in the form of an RNA/RNA, DNA/DNA or DNA/RNA hybrid, and the use of a double-stranded oligonucleotide structure, which comprises the double-stranded oligonucleotide, and nanoparticles, for preventing or treating obesity.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 2, 2023
    Inventors: Jun Hong PARK, Han-Oh PARK, Sung Il YUN, Tae Rim KIM, Soo Hyun HWANG, Kang SONG, Sang Hyuk JUNG, Jangseon KIM, Mi Sun LEE, Soonja CHOI, Seung Seob SON
  • Publication number: 20230060603
    Abstract: A method of using a processing oven may include disposing at least one substrate in a chamber of the oven and activating a lamp assembly disposed above them to increase their temperature to a first temperature. A chemical vapor may be admitted into the chamber above the at least one substrate and an inert gas may be admitted into the chamber below the at least one substrate. The temperature of the at least one substrate may then be increased to a second temperature higher than the first temperature and then cooled down.
    Type: Application
    Filed: July 25, 2022
    Publication date: March 2, 2023
    Applicant: Yield Engineering Systems, Inc.
    Inventors: Lei Jing, M Ziaul Karim, Kenneth Sautter, Kang Song
  • Patent number: 11465225
    Abstract: A method of using a solder reflow oven can include disposing at least one substrate including solder in a chamber of the oven. The method can include decreasing a pressure of the chamber to a first pressure between about 0.1-50 Torr. After decreasing the pressure of the chamber, the temperature of the at least one substrate can be increased to a first temperature. Formic acid vapor can be admitted into the chamber above the at least one substrate while nitrogen is discharged into the chamber below the at least one substrate. The method can also include removing at least a portion of the formic acid vapor from the enclosure. After the removing step, the temperature of the at least one substrate can be further increased to a second temperature higher than the first temperature. The at least one substrate can be maintained at the second temperature for a first time. And then, the at least one substrate can be cooled.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: October 11, 2022
    Assignee: YIELD ENGINEERING SYSTEMS, INC.
    Inventors: Lei Jing, M Ziaul Karim, Kenneth Sautter, Kang Song
  • Patent number: 11180204
    Abstract: A track-type moving device having one or more track mechanisms. The track mechanism may include a guide wheel, a driving wheel, a track, and/or a tensioning mechanism. The tensioning mechanism may include an adjusting member and/or an elastic member. The elastic member may provide a driving force that enables the adjusting member to move.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 23, 2021
    Assignee: Positec Power Tools (Suzhou) Co., Ltd.
    Inventors: Yuanzhong Ran, Kang Song
  • Patent number: 11070361
    Abstract: Provided is a block generation method in blockchain-based system. The block generation method comprises calculating, by a first blockchain node among the plurality of blockchain nodes, a first node score, propagating, by the first blockchain node, the first node score to the plurality of blockchain nodes, receiving, by the first blockchain node, a delegation of a block generation authority from a second blockchain node among the plurality of blockchain nodes, the second blockchain node having received the first node score and initiating, by the first blockchain node, generation of a new block based on a determination that a block generation node condition, that is based on the block generation authority, has been satisfied.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Jeong Ho Kim, Min Kang Song, Seung Won Son, Doo Yeol Kim, Seung Jun Ko, Yeong Min Seo