Patents by Inventor Kang Tae Park

Kang Tae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8164193
    Abstract: The present invention relates to a metal wiring of a semiconductor device and a method for the same, and is directed to disclose a technique forming an additional conductive layer within the metal line, which acts as an etching barrier to increase the etching margin and to improve the RC characteristics between the metal lines, which can prevent the Cu migration.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang Tae Park
  • Publication number: 20110031626
    Abstract: The present invention relates to a metal wiring of a semiconductor device and a method for the same, and is directed to disclose a technique forming an additional conductive layer within the metal line, which acts as an etching barrier to increase the etching margin and to improve the RC characteristics between the metal lines, which can prevent the Cu migration.
    Type: Application
    Filed: December 28, 2009
    Publication date: February 10, 2011
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kang Tae PARK
  • Patent number: 7056841
    Abstract: A method for fabricating a semiconductor device for reducing coupling noise resulting from high integration of devices, comprises the steps of forming a plurality of metal wiring leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate having a predetermined under layer; forming an insulating interlayer on an entire surface of the semiconductor substrate so that the metal wiring leads are covered with the insulating interlayer; and ion-implanting conductive impurities having a plurality opposite to each other into side end layers of the insulating interlayer disposed between the metal wiring leads so as to reduce the internal charges electrified due to an applied external electric field.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 6, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kang Tae Park