Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

Abstract: A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in one of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

Abstract: In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

Abstract: A ferroelectric random access memory (FRAM) device includes a memory cell array including a plurality of FRAM cells connected to a first bit line and a reference cell connected to a second bit line. The device also includes a sense amplifier circuit configured to evaluate an amount of charges induced in a FRAM cell at a first mode and sense data stored in the FRAM cell at a second mode, wherein the sense amplifier circuit comprises a reference voltage generator configured to output an externally applied voltage as a reference voltage at the first mode, and output the reference voltage in response to a voltage applied to the second bit line from the reference cell and a voltage charged to an offset node at the second mode, and an amplifier circuit configured to sense and amplify a difference between a voltage applied to the first bit line from a selected FRAM cell and the reference voltage.

Abstract: A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

Abstract: A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

Abstract: A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

Abstract: A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in owe of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

Abstract: A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.

Abstract: A ferroelectric random access memory (FRAM) device includes a memory cell array including a plurality of FRAM cells connected to a first bit line and a reference cell connected to a second bit line. The device also includes a sense amplifier circuit configured to evaluate an amount of charges induced in a FRAM cell at a first mode and sense data stored in the FRAM cell at a second mode, wherein the sense amplifier circuit comprises a reference voltage generator configured to output an externally applied voltage as a reference voltage at the first mode, and output the reference voltage in response to a voltage applied to the second bit line from the reference cell and a voltage charged to an offset node at the second mode, and an amplifier circuit configured to sense and amplify a difference between a voltage applied to the first bit line from a selected FRAM cell and the reference voltage.

Abstract: A ferroelectric random access memory (FRAM) device and a driving method thereof are provided that reduce data loss in an operation of the FRAM device. A power supply supplies a power source to the memory device. A power detection circuit detects a voltage level of the power supply and generates a detection signal when the power source has an off state. In an internal chip enable (ICE) signal generation circuit, an ICE signal is disabled to stop operation of the memory device when the ICE signal is enabled and the detection signal is applied at a first time point, and an enabled state of the ICE signal is maintained when the detection signal is applied at a second time point, wherein the operation of the FRAM device continues by control signals generated from the ICE signal.

Abstract: A FeRAM device and a writing section control method therefor, in which the device includes a memory cell constructed of one access transistor and one ferroelectric capacitor; and a writing control circuit for controlling a first writing section to write data of a first logic state in the memory cell and a second writing section to write data of a second logic state different from the first logic state, in response to an external clock signal. Thus a stabilized write operation can be performed and a reliability of data stored in the memory cell can be tested.

Abstract: A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

Abstract: A reference voltage generating apparatus and a driving method therefor are provided. The method of driving the reference voltage generating apparatus for supplying a reference voltage to read data from a ferroelectric memory cell including a ferroelectric capacitor and an access transistor comprises: re-storing, in a reference cell, data equal to data stored in the reference cell, in response to a first control signal, and generating a reference voltage, in the re-stored reference cell, in response to a second control signal, to compare the reference voltage with a voltage corresponding to data stored in the ferroelectric memory cell and to read the data stored in the ferroelectric memory cell. The reference cell includes a ferroelectric capacitor and an access transistor.