Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock.

Abstract: A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal.

Abstract: A pixel clock generator is provided. The pixel clock generator includes a phase-locked-loop (PLL) circuit that generates, from an oscillation signal having a first frequency of tens of MHz, a multi-phase oscillation signal having a second frequency of several GHz; and a frequency/phase adjusting circuit that synchronizes the multi-phase oscillation signal with a horizontal sync signal to generate a first oscillation signal, frequency-divides the first oscillation signal to generate a second oscillation signal, and adjusts a phase of the second oscillation signal to generate the pixel clock.

Abstract: A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal.