Abstract: Proposed is a detachable mooring system for an offshore structure, including a first tension adjuster connected to an offshore structure, and blocking a pulling chain from proceeding from an outlet of a body toward an inlet, a second tension adjuster connected to one end of the pulling chain and blocking the pulling chain from proceeding from an outlet of a body toward an inlet, a mooring chain having a first longitudinal end connected to one surface of the second tension adjuster body and having a second longitudinal end connected to an anchor on the seabed, a first lead rope having one longitudinal end connected to one end of the pulling chain discharged out through the first tension adjuster outlet, and a second lead rope having one longitudinal end connected to the second tension adjuster body.

Abstract: The present disclosure relates to a portable printer including a main body in a portable form which is capable of accommodating a cartridge having a nozzle for delivering a printing material to a target having a soft or hard surface, a seating part which is provided to be exposed to an outside from a lower portion of the main body to face the surface of the target and at least partially surrounds the nozzle, a roller provided respectively at the front and rear of the nozzle at the lower portion of the main body with respect to a direction in which the main body moves along the surface of the target to deliver the printing material to the target, and a printing adjustment unit configured to adjust a height difference between the nozzle and the roller to adjust a height difference between the nozzle and the surface of the target.

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

Abstract: A display device includes a display area, a peripheral area disposed outside the display area, and a sealing area disposed outside the peripheral area, a first base substrate, a second base substrate facing the first base substrate, a color filter layer disposed under the first base substrate, a bank layer disposed under the color filter layer, and a sealing member disposed between the bank layer and the second base substrate in the sealing area. The bank layer includes bank patterns defining an opening disposed at least in the sealing area, and the sealing member fills the opening. Each of the bank patterns includes a first surface adjacent to the color filter layer and a second surface opposite to the first surface and adjacent to the sealing member. A width of the second surface is greater than a width of the first surface.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: Apparatuses and techniques for implementing a data-transfer test mode are described. The data-transfer test mode refers to a mode in which the transfer of data from an interface die to a linked die can be tested prior to connecting the interface die to the linked die. In particular, the data-transfer test mode enables the interface die to perform aspects of a write operation and output a portion of write data that is intended for the linked die. With the data-transfer test mode, testing (or debugging) of the interface die can be performed during an earlier stage in the manufacturing process before integrating the interface die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the data-transfer test mode can be executed independent of whether the interface die is connected to the linked die.

Abstract: This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.

Abstract: Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.

Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: A self-cleaning device comprises at least one first electrode disposed on a solid material layer, a first dielectric layer disposed on the first electrode, a hydrophobic layer disposed on the first dielectric layer, and at least one mechanical oscillation unit. Electrical oscillation for oscillating a droplet in a horizontal direction is generated by applying a first electric signal to the first electrode, thereby merging droplets formed on the hydrophobic layer, the mechanical oscillation unit moves the merged droplets in a specific direction or atomizes the merged droplets to remove the merged droplets by generating mechanical oscillation for oscillating the droplet in a vertical direction, and each of the droplets has a volume smaller than 3 ?l, and new droplet having a volume more than 3 ?l is generated by the merging.

Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

Abstract: Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Abstract: Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.

Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.