Abstract: A semiconductor device includes: a vertical transport field-effect transistor (VTFET) device including a bottom source/drain (S/D) epitaxial layer, a vertical fin channel formed on the bottom S/D epitaxial layer, and a top S/D epitaxial layer formed on the vertical fin channel. The bottom S/D epitaxial layer has an asymmetric profile in cross-section where a first side of the vertical fin channel is aligned with a first side of the bottom S/D epitaxial layer, and the bottom S/D epitaxial layer has a stepped profile that extends beyond a second edge of the vertical fin channel.

Abstract: A method includes providing a substrate having an N+ type layer; forming a P type region in the N+ type layer disposed within the N+ type layer; forming a first deep trench isolation structure extending through a silicon layer and into the N+ type layer to a depth that is greater than a depth of the P type layer; forming a dynamic RAM FET in the silicon layer, forming a first logic/static RAM FET in the silicon layer above the P type region, the P type region being functional as a P-type back gate of the first logic/static RAM FET; and forming a first contact through the silicon layer and an insulating layer to electrically connect to the N+ type layer and a second contact through the silicon layer and the insulating layer to electrically connect to the P type region.

Abstract: A transistor structure includes a channel located in an extremely thin silicon on insulator (ETSOI) layer and disposed between a raised source and a raised drain, a gate structure having a gate conductor disposed over the channel and between the source and the drain, and a gate spacer layer disposed over the gate conductor. The raised source and the raised drain each have a facet that is upwardly sloping away from the gate structure. A lower portion of the source and a lower portion of the drain are separated from the channel by an extension region containing a dopant species diffused from a dopant-containing glass.

Abstract: A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.