Patents by Inventor Kanji Mizuno

Kanji Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11546421
    Abstract: A connection management device is communicatively connected to a plurality of server devices. A receiver receives from a terminal device a request for connection to one of the plurality of server devices. A location information extractor extracts, from the request for connection, location information indicating a location where the terminal device exists. A region determiner determines, based on the extracted location information, a region where the terminal device exists. A connection destination determiner determines, based on the determined region, which of the plurality of server devices is the server device to which the terminal device is to connect. A transmitter transmits to the determined server device the request for connection received from the terminal device.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 3, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Nakajima, Kanji Mizuno, Masayuki Komatsu
  • Publication number: 20220224556
    Abstract: A connection management device is included in a terminal device, which is communicatively connected to a plurality of server devices. A location information acquirer acquires location information indicating a location where the terminal device exists. A region determiner determines based on the acquired location information, a region where the terminal device exists. A connection destination determiner determines, based on the determined region, which of the plurality of server devices is the server device to which the terminal device is to connect. A transmitter transmits to the determined server device a request for connection to connect to the server device.
    Type: Application
    Filed: May 30, 2019
    Publication date: July 14, 2022
    Inventors: Yoshinori NAKAJIMA, Kanji MIZUNO, Masayuki KOMATSU, Naoki TAMURA
  • Publication number: 20220159066
    Abstract: A connection management device is communicatively connected to a plurality of server devices. A receiver receives from a terminal device a request for connection to one of the plurality of server devices. A location information extractor extracts, from the request for connection, location information indicating a location where the terminal device exists. A region determiner determines, based on the extracted location information, a region where the terminal device exists. A connection destination determiner determines, based on the determined region, which of the plurality of server devices is the server device to which the terminal device is to connect. A transmitter transmits to the determined server device the request for connection received from the terminal device.
    Type: Application
    Filed: April 3, 2019
    Publication date: May 19, 2022
    Inventors: Yoshinori NAKAJIMA, Kanji MIZUNO, Masayuki KOMATSU
  • Publication number: 20220038600
    Abstract: An information processing device (1) includes a signal receiver (12), an entry information inputter (16), a storage (11), and a document information generator (15). The signal receiver (12) receives a signal representing a transfer request to transfer data. The entry information inputter (16) inputs entry information that is information to be entered into a transfer procedure document that is a document for a transfer procedure with respect to the transfer request. The storage (11) stores the entry information inputted by the entry information inputter (16).
    Type: Application
    Filed: December 18, 2018
    Publication date: February 3, 2022
    Inventors: Yoshinori NAKAJIMA, Kanji MIZUNO, Masayuki KOMATSU, Toru INADA
  • Publication number: 20090057417
    Abstract: The present invention realizes a card on which a secure IC chip (a first semiconductor chip) that operates on both of a high power source voltage and a low power source voltage, and a nonvolatile semiconductor storage chip that operates on the lower power source voltage are mounted. Means for operating the card without exerting an adverse influence of the nonvolatile semiconductor storage chip when the high power source voltage is supplied is realized. A card has a voltage supply interrupting unit which is coupled to a power source terminal to which a first power source voltage and a second power source voltage higher than the first power source voltage are supplied, and a grounding terminal to which a grounding voltage is supplied. The voltage supply interrupting unit, when the first power source voltage is supplied, supplies voltage to a nonvolatile semiconductor storage chip and, when the second power source voltage is supplied, stops supplying the voltage to the nonvolatile semiconductor storage chip.
    Type: Application
    Filed: August 26, 2008
    Publication date: March 5, 2009
    Inventors: Minoru SHINOHARA, Takeshi Miura, Kanji Mizuno, Shigemasa Shiota, Masayuki Suzuki, Hirotaka Nishizawa
  • Publication number: 20020060352
    Abstract: The semiconductor integrated circuit has a TaN layer as a trimming device. Current trimming and laser trimming can be performed on this TaN layer. A part of a metal wiring layer is removed to expose a TaN layer functioning as a metal barrier of the metal wiring layer provided on the TaN layer, thereby obtaining a TaN single layer portion. The TaN single layer portion is used as a resistor for trimming functioning as a fuse.
    Type: Application
    Filed: April 11, 2001
    Publication date: May 23, 2002
    Inventor: Kanji Mizuno
  • Patent number: 5634105
    Abstract: In a semiconductor memory device in which row and column address signals are serially supplied using a multiplexer or serial address signals are supplied without using a multiplex, a RAM interface is provided which easily makes it possible to replace a DRAM with a SRAM. A memory IC which is formed by a DRAM is changed to a SRAM, and a resulting SRAM memory IC is controlled using a logic IC 10 which is originally constructed for use with the original DRAM memory IC. Between the logic IC and the SRAM memory IC, a RAM interface is disposed. According to the present invention, it is possible to divide row-column address signals which are supplied in serial form into row address signals and column address signals and to modify a control signal which controls a dynamic RAM to control a static RAM.
    Type: Grant
    Filed: July 21, 1994
    Date of Patent: May 27, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kanji Mizuno
  • Patent number: 5194828
    Abstract: In a second PLL circuit 200, a phase comparator 13 compares the phase of a clock B' from a frequency divider 11 with the phase of a clock A' from a first PLL circuit 100 to transmit a comparison result to low pass filters X and Y in a filter circuit 14. A phase shift detector 12 detects a phase shift between the clocks A' and B' to output a detection signal E corresponding to the phase shift. A selector 15 selectively outputs an output of either the low pass filter X or Y in response to the detection signal E to input it to a VCXO 10. When the phase shift between the clocks A' and B' exceeds a predetermined value, the low pass filter Y having a high cut-off frequency is selected, whereby the second PLL circuit 200 responds rapidly, and the clock B' follows the clock A' quickly.
    Type: Grant
    Filed: November 5, 1991
    Date of Patent: March 16, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hisao Kato, Kanji Mizuno