Patents by Inventor Kanji Sugino

Kanji Sugino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8932882
    Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: January 13, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Katsushi Takano, Hiroaki Izumi, Kanji Sugino
  • Publication number: 20110250707
    Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first group identifier allocated to a first group of semiconductor wafers is detected. The first group of semiconductor wafers includes a first semiconductor wafer to be processed first among the first group. A first processor of a plurality of processors, which process respective ones of the first group of semiconductor wafers, are determined based on the first group identifier. The first processor is used for processing the first semiconductor wafer. The first semiconductor wafer is supplied to the first processor.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 13, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Katsushi TAKANO, Hiroaki IZUMI, Kanji SUGINO
  • Publication number: 20080180647
    Abstract: The focus monitor mark of the present invention includes two dot groups formed with a plurality of dots comprising a resist that is formed in a protruding manner with respect to a wafer surface, and a measurement region. The mark includes a dot pattern mark in which dot groups are arranged so that the dimensions of each dot increase in accordance with an increase in the distance of the dot from the measurement region, two hole groups comprising a plurality of holes formed in the resist on the wafer surface, and measurement region 3. The mark has a hole pattern mark in which each hole is arranged so that the dimensions of each hole increase in accordance with an increase in a distance of the hole from the measurement region.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 31, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Kanji SUGINO
  • Patent number: 6566040
    Abstract: First, a hole pattern or a separation pattern of a first resist that is capable of supplying acid is formed on a semiconductor substrate. Then, a crosslinked film (organic frame) is formed on the side wall of the first resist pattern to obtain a resist pattern having a reduced hole diameter or separation width. Then, the hole diameter or the separation width is further reduced by causing thermal reflow of the crosslinked film. Finally, the semiconductor substrate is etched by using a resulting resist pattern as a mask.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: May 20, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering Corporation
    Inventors: Kanji Sugino, Takeo Ishibashi, Takayuki Shoya
  • Patent number: 6180320
    Abstract: There is described a method of stably manufacturing a fine resist pattern narrower than the wavelength of exposing light from a stepper. Under the method, a resist pattern is formed on a semiconductor substrate through use of an acid catalyst chemically-amplified photoresist, and an organic film which includes an acid or which produces an acid on exposure to light is formed on the surface of the semiconductor substrate including the resist pattern. The organic film is then subjected to a heat treatment to thereby diffuse an acid. The surface layer of the resist pattern is made soluble in an alkaline developer, and the surface layer of the resist pattern is removed through use of the alkaline developer. As a result, a fine resist pattern is formed.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: January 30, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takayuki Saito, Takeo Ishibashi, Toshiyuki Toyoshima, Kanji Sugino, Naoki Yasuda, Tadashi Miyagi