Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

Abstract: A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions.

Abstract: A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract: An integrated circuit device includes a fin at least partially embedded in a shallow trench isolation (STI) region and extending between a source and a drain. The fin is formed from a first semiconductor material and having a trimmed portion between first and second end portions. A cap layer, which is formed from a second semiconductor material, is disposed over the trimmed portion of the fin to form a high mobility channel. A gate electrode structure is formed over the high mobility channel and between the first and second end portions.

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.