Patents by Inventor Kaori Ikada

Kaori Ikada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PHOTOELECTRIC CONVERSION DEVICE AND LIGHT-EMITTING AND LIGHT-RECEIVING APPARATUS
    Publication number: 20230354625
    Abstract: A photoelectric conversion device in which an increase in driving voltage is inhibited is provided. The photoelectric conversion device includes a first electrode, a second electrode, and an organic compound layer; the organic compound layer is positioned between the first electrode and the second electrode; the organic compound layer includes a first layer; a structure body including projections is included between the first layer and the second electrode; and the structure body contains a first organic compound.
    Type: Application
    Filed: April 25, 2023
    Publication date: November 2, 2023
    Inventors: Daisuke KUBOTA, Akio YAMASHITA, Kazuya SUGIMOTO, Taisuke KAMADA, Sachiko KAWAKAMI, Kazuki KAJIYAMA, Yasutaka NAKAZAWA, Kaori IKADA
  • Regulator circuit and RFID tag including the same
    Patent number: 9092042
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: July 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tsuji, Kaori Ikada
  • Regulator Circuit and RFID Tag Including the Same
    Publication number: 20130335056
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 19, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki INOUE, Kiyoshi KATO, Shuhei NAGATSUKA, Koichiro KAMATA, Tsutomu MURAKAWA, Takahiro TSUJI, Kaori IKADA
  • Regulator circuit and RFID tag including the same in wireless communication to improve noise margin
    Patent number: 8587286
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: November 19, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
  • Regulator circuit and RFID tag including the same in wireless communication to improve noise margin
    Patent number: 8456148
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
  • Regulator circuit and RFID tag including the same in wireless communication to improve noise margin
    Patent number: 8344719
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada
  • Regulator Circuit and RFID Tag Including the Same
    Publication number: 20100181985
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 22, 2010
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tuji, Kaori Ikada