Abstract: A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing.

Abstract: A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing.

Abstract: An output port circuit includes a plurality of output buffers; a plurality of first holding circuits configured to hold output data to be outputted to the plurality of output buffers; a plurality of second holding circuits configured to hold output data to be outputted to the plurality of first holding circuits; and a plurality of third holding circuits configured to hold bit pattern data for individually setting whether the output data of the plurality of second holding circuits are latched by the plurality of first holding circuits. Data input to the plurality of second holding circuits and data input to the plurality of third holding circuits are controlled at a same timing.

Abstract: A microcomputer has flash memory having at least two data areas, others of which can be written while one is being read, and substitute RAM which is used when adjusting control data prior to adjustment (pre-adjustment control data) which is stored in for example one of the data areas; the CPU controls equipment to be controlled by executing a program in a program storage portion using control data in one of the data areas. In adjustment processing of the control data, the control data in one of the data areas is copied to RAM and adjusted to values appropriate to the equipment to be controlled, and the adjusted control data is written to another data area, after which the addresses in a memory map of the two data areas are swapped. Subsequently, the CPU controls the equipment using the adjusted control data which physically is stored in the other data area.

Abstract: There is provided a computer that can safely rewrite any one of the areas where a boot program is stored with fewer actions in the self-mode. A nonvolatile memory is divided into a plurality of areas, each of which is separately erasable and includes a user area and a boot area designation flag indicating whether the corresponding user area is specified as a boot area. An area designation flag specifies the user area containing a boot program among a plurality of user areas. A CPU sets the value of the area designation flag based on the values of a plurality of boot area designation flags. When a system is started, the user area including the program for starting the operation of the CPU is determined based on the value of the area designation flag.

Abstract: There is provided a computer that can safely rewrite any one of the areas where a boot program is stored with fewer actions in the self-mode. A nonvolatile memory is divided into a plurality of areas, each of which is separately erasable and includes a user area and a boot area designation flag indicating whether the corresponding user area is specified as a boot area. An area designation flag specifies the user area containing a boot program among a plurality of user areas. A CPU sets the value of the area designation flag based on the values of a plurality of boot area designation flags. When a system is started, the user area including the program for starting the operation of the CPU is determined based on the value of the area designation flag.

Abstract: A coincidence signal is output when coincidence of a timer counter with the set value of a comparison register is detected by a coincidence detecting circuit and the coincidence signal is input to the external CPU as an interruption signal to execute a CPU to start an interruption routine. In the interruption routine, a reverse enable flag is set, a flag indicating permission to reverse an output signal when the value of a key counter is larger than the value of a buzzer counter and a reverse enable flag is set, a flag indicating prohibition of reversing the output signal when the value of the key counter is smaller than that of the buzzer counter.

Abstract: The invention provides a bus driver failure detection system which facilitates detection of a failure of a bus driver from which data are sent out to a bus. The bus driver failure detection system includes a plurality of bus drivers for sending out signals to a single bus, at least one receiver connected to the bus, and an impedance control circuit for controlling the bus so that, upon testing, the bus does not exhibit a high impedance state. The impedance control circuit may be constructed as a circuit which holds a value of the bus in response to a test signal.

Abstract: A semiconductor device has a precharge control circuit for generating a precharge control signal, the precharge control signal being at an active level when all word lines do not indicate a high level and being at an inactive level when an access control signal (read control signal or write control signal) is input to the precharge control circuit for controlling a precharge circuit for precharging bit lines to a predetermined voltage.