Patents by Inventor Kaoru Awaka

Kaoru Awaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7315879
    Abstract: A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110a) connected to at least one of the Booth encoder cells (104a) and a plurality of Wallace tree cells (112a) connected to at least one of the Booth decoder cells (110a). Moreover, at least one first Wallace tree cell (112a1) or at least one first Booth decoder cell (110a1), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell (112a2) or at least one second Booth decoder cell (110a2), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module (100) includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: January 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Kaoru Awaka, Hiroshi Takahashi, Shigetoshi Muramatsu, Akihiro Takegama
  • Patent number: 7039667
    Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: May 2, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Kaoru Awaka, Yutaka Toyonoh, Hiroshi Takahashi
  • Patent number: 7035893
    Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Kaoru Awaka, Yutaka Toyonoh, Hiroshi Takahashi
  • Publication number: 20050177611
    Abstract: The objective of this invention is to provide a type of addition circuit that can perform addition at a high speed without increasing power consumption, as well as a type of multiplication circuit and a type of multiplication/addition circuit having said addition circuit as the last step. It has a characteristic feature that the delay in a signal input from a Wallace tree to the addition circuit in the last step is maximum in the intermediate bit range, and it is smaller in the lower and upper bit ranges. In the lower bit range, addition is performed by means of 1-level carry increment adder 1 with a larger delay in carry propagation to the upper place. In the intermediate bit range, addition is performed by means of 2-level carry increment adder 1 having a carry propagation speed higher than that in said lower bit range. In the upper bit range, addition is performed by means of high-speed carry select adder 3.
    Type: Application
    Filed: December 14, 2004
    Publication date: August 11, 2005
    Inventors: Kaoru Awaka, Akihiro Takegama, Yutaka Toyonoh, Shigetoshi Muramatsu
  • Publication number: 20050068059
    Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.
    Type: Application
    Filed: October 12, 2004
    Publication date: March 31, 2005
    Inventors: Hiroshi Takahashi, Akihiro Takegama, Yutaka Toyonoh, Kaoru Awaka, Tsuyoshi Tanaka, Rimon Ikeno
  • Patent number: 6864708
    Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: March 8, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Takahashi, Akihiro Takegama, Yutaka Toyonoh, Kaoru Awaka, Tsuyoshi Tanaka, Rimon Ikeno
  • Publication number: 20050044125
    Abstract: A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight.
    Type: Application
    Filed: September 30, 2004
    Publication date: February 24, 2005
    Inventors: Kaoru Awaka, Yutaka Toyonoh, Hiroshi Takahashi
  • Patent number: 6850103
    Abstract: This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: February 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Rimon Ikeno, Kaoru Awaka, Tsuyoshi Tanaka, Hiroshi Takahashi, Yutaka Toyonoh, Akihiro Takegama
  • Patent number: 6741098
    Abstract: A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: May 25, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Takahashi, Yutaka Toyonoh, Akihiro Takegama, Osamu Handa, Rimon Ikeno, Kaoru Awaka, Tsuyoshi Tanaka
  • Publication number: 20040061135
    Abstract: This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventors: Rimon Ikeno, Kaoru Awaka, Tsuyoshi Tanaka, Hiroshi Takahashi, Yutaka Toyonoh, Akihiro Takegama
  • Publication number: 20040049529
    Abstract: A partial product generator and a multiplier are configured to provide increased operation speed. First encoder Ej1 generates control code A1 and control code A2 that determine the fold (1-fold or 2-fold) of the partial product with respect to the multiplicand corresponding to bit Y2j and bit Y2j−1 of the multiplier. Second encoder Ej2 generates control code/ZDT that determines whether the partial product has value “0” corresponding to bit Y2j and Y2j+1 of the multiplier and second control code A2. Third encoder Ej3 generates control code Sgn and control code/Sgn that determine the sign of the partial product corresponding to bit Y2j+1 of the multiplier and bit inversion signal AsX. Since control code/ZDT with a longer generation time is treated in the latter section circuit of bit circuit Pji, it is possible to realize high speed for the process.
    Type: Application
    Filed: June 10, 2003
    Publication date: March 11, 2004
    Inventors: Kaoru Awaka, Yutaka Toyonoh, Hideyuki Fukuhara
  • Patent number: 6603328
    Abstract: The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: August 5, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroshi Takahashi, Osamu Handa, Akihiro Takegama, Yutaka Toyonoh, Kaoru Awaka, Rimon Ikeno, Tsuyoshi Tanaka
  • Publication number: 20030067318
    Abstract: The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows Iddq test to determine whether it is passed or defective. Logic circuit 10 composed of low threshold voltage transistors and switching circuit 20 composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit 10. On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of Iddq test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P1 and P2.
    Type: Application
    Filed: October 10, 2001
    Publication date: April 10, 2003
    Inventors: Hiroshi Takahashi, Osamu Handa, Akihiro Takegama, Yutaka Toyonoh, Kaoru Awaka, Rimon Ikeno, Tsuyoshi Tanaka
  • Publication number: 20030025130
    Abstract: A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuit 20 is provided between logic circuit 10 and source voltage Vdd supply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MP0 of switching circuit 20, and bias voltage VB equal to or slightly lower than source voltage Vdd is applied to its channel region in order to reduce the threshold voltage of transistor MP0 and increase its current driving capability.
    Type: Application
    Filed: July 22, 2002
    Publication date: February 6, 2003
    Inventors: Hiroshi Takahashi, Akihiro Takegama, Yutaka Toyonoh, Kaoru Awaka, Tsuyoshi Tanaka, Rimon Ikeno
  • Publication number: 20020190752
    Abstract: A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P2 and P3 which have different voltages applied to the respective sources and the mode control signal input to the [respective] gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby.
    Type: Application
    Filed: June 19, 2001
    Publication date: December 19, 2002
    Inventors: Hiroshi Takahashi, Yutaka Toyonoh, Akihiro Takegama, Osamu Handa, Rimon Ikeno, Kaoru Awaka, Tsuyoshi Tanaka
  • Patent number: 6468848
    Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: October 22, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kaoru Awaka, Masashi Hashimoto, Masaaki Aoki
  • Publication number: 20020116433
    Abstract: A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110a) connected to at least one of the Booth encoder cells (104a) and a plurality of Wallace tree cells (112a) connected to at least one of the Booth decoder cells (110a). Moreover, at least one first Wallace tree cell (112a1) or at least one first Booth decoder cell (110a1), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell (112a2) or at least one second Booth decoder cell (110a2), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module (100) includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.
    Type: Application
    Filed: September 27, 2001
    Publication date: August 22, 2002
    Inventors: Kaoru Awaka, Hiroshi Takahashi, Shigetoshi Muramatsu, Akihiro Takegama
  • Publication number: 20020096723
    Abstract: An integrated circuit having a primary transistor (12, 22, 32, 42, 52) and an associated secondary transistor (15, 25, 35, 45, 55) for dynamically varying the voltage of the body node (B) of the primary transistor (12, 22, 32, 42, 52) responsive to the gate voltage of the primary transistor (12, 22, 32, 42, 52) is disclosed. According to the disclosed embodiments of the invention, each of the primary transistor (12, 22, 32, 42, 52) and secondary transistor (15, 25, 35, 45, 55) are bulk transistors, formed at a surface of a substrate (11), where the secondary transistor (15, 25, 35, 45, 55) has a much smaller channel width than that of the primary transistor (12, 22, 32, 42, 52), to enhance the transient frequency of the device. In each case, the secondary transistor (15, 25, 35, 45, 55) has its source-drain path connected between the gate (G) and the body node (B) of the primary transistor (12, 22, 32, 42, 52).
    Type: Application
    Filed: December 7, 2000
    Publication date: July 25, 2002
    Inventor: Kaoru Awaka
  • Patent number: 6307233
    Abstract: A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: October 23, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Kaoru Awaka, Masashi Hashimoto, Masaaki Aoki