Abstract: The object is to provide a novel organism identification method which can be used as an alternative method to a conventional organism identification method which utilizes DNA and requires enormous labor. Developed is an organism identification method for determining whether or not an organism of interest is identical to a specific organism or a progeny thereof, which is characterized by introducing a DNA tag(s) in advance into a cell(s) of the specific organism, or a parasite or a symbiont with the specific organism, and determining whether or not the organism of interest is identical to the specific organism or a progenitor thereof based on the detection or non-detection of the DNA tag in DNA extracted from the organism of interest, or the parasite or the symbiont with the organism of interest.

Abstract: A power semiconductor module comprises a circuit board made of an insulating substrate of good thermal conductivity formed with interconnect patterns, a plurality of power semiconductor chips mounted on the circuit board, bonding wires for electrically connecting the semiconductor chips and the interconnect patterns, outer lead terminals fixed to the interconnect patterns, and a resin layer for covering at least the chip mounted surface of the circuit board in its entirety so that the tip of each of the outer lead terminals is exposed.

Abstract: A power semiconductor module comprises a circuit board made of an insulating substrate of good thermal conductivity formed with interconnect patterns, a plurality of power semiconductor chips mounted on the circuit board, bonding wires for electrically connecting the semiconductor chips and the interconnect patterns, outer lead terminals fixed to the interconnect patterns, and a resin layer for covering at least the chip mounted surface of the circuit board in its entirety so that the tip of each of the outer lead terminals is exposed.

Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semiconductor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.

Abstract: A trimming resistor element includes a high-resistance film of high resistivity formed on an insulation film on the main surface of a substrate, and a low-resistance region which is formed by selectively subjecting the high-resistance film to a predetermined process so as to lower the resistivity thereof. A resultant resistance of the low-resistance region and the high-resistance film can be adjusted by selectively cutting off part of the low-resistance region.

Abstract: A trimming element comprises (a) a medium layer, (b) a pair of electrodes connected to the medium layer, and (c) an alloy layer, which is formed of metal of the electrodes and material of the medium layer and is created in the medium layer, for substantially short-circuiting the electrodes to each other. The alloy layer is obtained by applying a laser beam to the medium layer to heat a portion between the electrodes. The metal layer for substantially short-circuiting the electrodes is thus formed.

Abstract: A method of manufacturing a semiconductor device comprising the steps of bringing a mirror-polished surface of a first semiconductor substrate of a first conductivity type into contact with a mirror-polished surface of a second semiconductor substrate of a second conductivity type having an impurity concentration which is lower than that of said first conductivity type, in a clean atmosphere, and thermally heating said first and second semiconductor substrates so that they unite. Impurity is diffused from said first semicondutor substrate into said second semiconductor substrate, thereby forming a diffusion layer of a first conductivity type in said second semiconductor substrate. A total amount of impurity of said diffusion layer is 1.times.10.sup.13 /cm.sup.2 to 2.times.10.sup.15 /cm.sup.2, to form a pn junction in said second semiconductor substrate.

Abstract: A trimming process by a laser beam is disclosed. The trimming process comprises two steps. In a first step, a laser shield layer is formed over an untrimmed region of a trimmed material adjacent to a trimmed region. The laser shield layer has a higher heat conductivity than the trimmed material and a large reflectivity for laser beam. In a second step, the trimmed material is cut off. To cut off, a laser beam is applied onto the upper surface of the trimmed region of the trimmed material to vaporize the trimmed material in the trimmed region.

Abstract: A trimming resistor network includes first and second external connection terminals, a first resistor having two ends acting as first and second connection terminals, a first coupling body for connecting the first external connection terminal to the first connection terminal via series-connected resistors, a second coupling body for connecting the second external connection terminal to the second connection terminal directly or via series-connected resistors, and parallel trimming resistors having two ends respectively connected to the first and second coupling bodies. The combined resistance between the first and second external connection terminals is increased by substantially a preset amount each time one of the parallel trimming resistors is cut off.

Abstract: A protection circuit is provided for a planar transistor device. The protection circuit comprises a variable resistor device formed of a junction type field effect transistor. The resistor device is connected in series with the base of the planar transistor. The drain electrode of the J-FET is connected to the base of the planar transistor while the collector of the planar transistor is connected to the gate of the J-FET. Due to this interconnected scheme, base input resistance of the planar transistor is increased to reduce its base current when a high voltage is applied accidentally to the collector. The base current is not eliminated, however, and the device is protected but can still operate.