Patents by Inventor Kaoru Saigoh

Kaoru Saigoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090267185
    Abstract: A method of manufacturing a semiconductor device includes forming a wiring layer in a first insulating layer, forming a second insulating layer over the first insulating layer, forming a first conductive layer over the second insulating layer, forming a dielectric layer on the first conductive layer, forming a second conductive layer on the dielectric layer, selectively removing the second conductive layer to form an upper electrode on the dielectric layer, forming a first layer over the upper electrode and the dielectric layer, selectively removing the first layer, the dielectric layer, and the first conductive layer to form a lower electrode over which the dielectric layer and the first layer is entirely left, the upper electrode remaining partially over the lower electrode.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 29, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Tatsuro Osada, Kaoru Saigoh
  • Publication number: 20090243038
    Abstract: A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kouichi NAGAI, Kaoru Saigoh
  • Publication number: 20090160023
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: February 24, 2009
    Publication date: June 25, 2009
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20090008783
    Abstract: A semiconductor device is provided having a pad with an improved moisture blocking ability. The semiconductor device has: a circuit portion including a plurality of semiconductor elements formed on a semiconductor substrate; lamination of insulator covering the circuit portion, including a passivation film as an uppermost layer having openings; ferro-electric capacitors formed in the lamination of insulator; wiring structure formed in the lamination of insulator and connected to the semiconductor elements and the ferro-electric capacitors; pad electrodes connected to the wiring structure, formed in the lamination of insulator and exposed in the openings of the passivation film; a conductive pad protection film, including a Pd film, covering each pad electrode via the opening of the passivation film, and extending on the passivation film; and stud bump or bonding wire connected to the pad electrode via the conductive pad protection film.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 8, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru SAIGOH, Kouichi NAGAI
  • Publication number: 20080258260
    Abstract: A semiconductor device including a capacitor formed over a semiconductor substrate and including a lower electrode, a dielectric film formed over the lower electrode and an upper electrode formed over the dielectric film, an insulation film formed over the semiconductor substrate and the capacitor, and an electrode pad formed over the insulation film and including an alloy film of aluminum and magnesium.
    Type: Application
    Filed: May 28, 2008
    Publication date: October 23, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi NAGAI, Kaoru Saigoh
  • Publication number: 20080099855
    Abstract: A protective film (56) having a water/hydrogen blocking function is formed so as to cover the periphery of a pad electrode (54a) while being electrically isolated from the pad electrode. A material selected in the embodiment for composing the protective film is a highly moisture-proof material having a water/hydrogen blocking function considerably superior to that of the insulating material, such as palladium (Pd) or palladium-containing material, and iridium (Ir) or iridium oxide (IrOx: typically x=2) or an iridium- or iridium oxide-containing material. An FeRAM capable of reliably preventing water/hydrogen from entering inside, and of maintaining high performance of the ferroelectric capacitor structure (30) may be realized only by a simple configuration.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 1, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi NAGAI, Katsuhiro SATO, Kaoru SUGAWARA, Makoto TAKAHASHI, Masahito KUDOU, Kazuhiro ASAI, Yukimasa MIYAZAKI, Kaoru SAIGOH
  • Patent number: 7288799
    Abstract: A semiconductor device includes a semiconductor substrate, a circuit part formed on and above the semiconductor substrate, a passivation film covering the circuit part, an electrode pad provided outside the circuit part in such a manner that the electrode pad is exposed from the passivation film, and a guard ring pattern provided between the electrode pad and the circuit part such that the guard ring pattern surrounds the circuit part substantially. The guard ring pattern extends from a surface of the semiconductor substrate to the passivation film.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 30, 2007
    Assignee: Fujitsu Limited
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Patent number: 7205594
    Abstract: The present invention relates to a semiconductor device having capacitors. The configuration of the device includes: capacitor upper electrodes 14a, 14b formed via a dielectric film 13 on plate lines 12a that become capacitor lower electrodes; a conductive connecting sections 12b that are connected to one ends of the plate lines 12a and have contact regions; upper conductive patterns 14c that are formed between the contact regions and the edge of plate lines 12a on the dielectric film 13 on the conductive connecting sections 12b and are in the same layer as the capacitor upper electrodes 14a, 14b.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: April 17, 2007
    Assignee: Fujitsu Limited
    Inventor: Kaoru Saigoh
  • Publication number: 20070020803
    Abstract: An ultra-thin semiconductor chip of an FeRAM, which is miniaturized and highly integrated with characteristic degradation of a ferroelectric capacitor suppressed though a thin package structure is applied to the FeRAM is realized. The semiconductor chip is molded up by using a sealing resin with a filler content set at a value in a range of 90 weight % to 93 weight % to produce a package structure.
    Type: Application
    Filed: February 28, 2006
    Publication date: January 25, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20060220081
    Abstract: After a ferroelectric capacitor is formed, an Al wiring (conductive pad) connected to the ferroelectric capacitor is formed. Then, a silicon oxide film and a silicon nitride film are formed around the Al wiring. Thereafter, as a penetration inhibiting film which inhibits penetration of moisture into the silicon oxide film, an Al2O3 film is formed.
    Type: Application
    Filed: July 27, 2005
    Publication date: October 5, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Kouichi Nagai, Hitoshi Saito, Kaoru Sugawara, Makoto Takahashi, Masahito Kudo, Kazuhiro Asai, Yukimasa Miyazaki, Katsuhiro Sato, Kaoru Saigoh
  • Publication number: 20050212020
    Abstract: An insulation film (24) having a gradual inclination of a surface is formed by a high density plasma CVD method, an atmospheric pressure CVD method or the like, after a ferroelectric capacitor (23) is formed. Thereafter, an alumina film (25) is formed on the insulation film (24). According to the method, low coverage of the alumina film (25) does not become a problem, and the ferroelectric capacitor (23) is reliably protected.
    Type: Application
    Filed: May 20, 2005
    Publication date: September 29, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kazutoshi Izumi, Hitoshi Saito, Naoya Sashida, Kaoru Saigoh, Kouichi Nagai
  • Patent number: 6913970
    Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
  • Publication number: 20050127395
    Abstract: A semiconductor device includes a semiconductor substrate, a circuit part formed on and above the semiconductor substrate, a passivation film covering the circuit part, an electrode pad provided outside the circuit part in such a manner that the electrode pad is exposed from the passivation film, and a guard ring pattern provided between the electrode pad and the circuit part such that the guard ring pattern surrounds the circuit part substantially. The guard ring pattern extends from a surface of the semiconductor substrate to the passivation film.
    Type: Application
    Filed: April 30, 2004
    Publication date: June 16, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru Saigoh, Kouichi Nagai
  • Publication number: 20040173874
    Abstract: The present invention relates to a semiconductor device having capacitors. The configuration of the device includes: capacitor upper electrodes 14a, 14b formed via a dielectric film 13 on plate lines 12a that become capacitor lower electrodes; a conductive connecting sections 12b that are connected to one ends of the plate lines 12a and have contact regions; upper conductive patterns 14c that are formed between the contact regions and the edge of plate lines 12a on the dielectric film 13 on the conductive connecting sections 12b and are in the same layer as the capacitor upper electrodes 14a, 14b.
    Type: Application
    Filed: February 26, 2004
    Publication date: September 9, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Kaoru Saigoh
  • Patent number: 6777736
    Abstract: The semiconductor device having the capacitor comprises a plurality of switching elements formed on a semiconductor substrate 1 at a distance, a plurality of capacitors formed in areas between a plurality of switching elements formed in the first direction respectively and each having a lower electrode, a dielectric film and an upper electrode, first wirings for connecting the upper electrodes of the capacitors and the switching elements in the first direction on a one-by-one base, and second wirings formed over a part of the first wirings, the switching elements, and the capacitors to extend in the second direction that intersects with the first direction. Accordingly, the higher speed operation than the prior art can be achieved.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: August 17, 2004
    Assignee: Fujitsu Limited
    Inventors: Kaoru Saigoh, Hisashi Miyazawa, Hirokazu Yamazaki, Hideaki Suzuki
  • Publication number: 20040043518
    Abstract: There is provided such a structure that a first insulating layer, a conductive pattern, a second insulating layer, a capacitor Q, a third insulating layer, and a lower electrode leading wiring are formed sequentially on a semiconductor substrate, and a lower electrode of the capacitor is connected to an upper surface of the conductive pattern, and the lower electrode leading wiring is also connected electrically to the conductive pattern from its upper side.
    Type: Application
    Filed: March 20, 2003
    Publication date: March 4, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Kaoru Saigoh
  • Patent number: 6700147
    Abstract: There is provided such a structure that a first insulating layer, a conductive pattern, a second insulating layer, a capacitor Q, a third insulating layer, and a lower electrode leading wiring are formed sequentially on a semiconductor substrate, and a lower electrode of the capacitor is connected to an upper surface of the conductive pattern, and the lower electrode leading wiring is also connected electrically to the conductive pattern from its upper side.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: March 2, 2004
    Assignee: Fujitsu Limited
    Inventor: Kaoru Saigoh
  • Publication number: 20030089938
    Abstract: There is provided a semiconductor device which comprises capacitors having lower electrodes, which are formed of platinum on a first insulating film over a semiconductor substrate to have a contact region, and upper electrodes formed on the lower electrodes via a dielectric film respectively, a second insulating film formed on the capacitors, a hole formed in the second insulating film on the contact region of the lower electrode, and a wiring constructed by forming an underlying conductive film, a minimum thickness of which is thicker than 30 nm at a bottom of the hole, and an aluminum film sequentially, and formed from an inside of the hole to an upper surface of the second insulating film.
    Type: Application
    Filed: October 23, 2002
    Publication date: May 15, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Kaoru Saigoh, Nobutaka Ohyagi, Kouji Tani, Hisashi Miyazawa, Kazutaka Miura
  • Publication number: 20030080364
    Abstract: There are provided the steps of forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 1, 2003
    Applicant: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
  • Patent number: 6509593
    Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 21, 2003
    Assignee: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki