Abstract: A non-volatile semiconductor memory device has writing part (203, 205, 209) for writing data in a non-volatile memory cell in response to a write pulse, readout part (419) for reading out data stored in the memory cell, and verification part (207, 210; 417) for verifying to ensure that normal writing has been completed by reading data from the memory cell after each writing. The device repeats writings unless a normal writing can be confirmed by the verification part. At this time, the writing part can vary writing time and in a part of a sequence of repeating writing unless a normal writing can be confirmed, it sets writing time longer for the next writing action than that for one writing action. Since this setting is performed according to constant multiplication, constant increment, or constant multiplication of accumulated value, necessary time for obtaining normal data write can be reduced.

Abstract: A non-volatile semiconductor memory device comprises: a plurality of memory cells for electrically rewriting data; a programming and erasing section for executing data writing programs and data erasing operation for the memory cells; a verifying section for discriminating whether a data is written in or erased from one of the memory cells properly whenever data are written to or erased from the memory cells; and an automatic control section for enabling the programming and erasing section to execute the data writing program and erasing operation again whenever the verifying section discriminates that data is not properly written to or erased from one of the memory cells, the data writing program or erasing operation being executed repeatedly by the number of times less than a user-defined maximum program execution or erasing operation number applied externally from the outside of the memory device. Further, the number of data writing and erasing operations can be outputted to the outside of the chip.

Abstract: In response to a plurality of address signal input from the outside in sequence, an erase information inputting section controls an erase information holding section corresponding to the batch erase block to be erased so as to hold an erase information data. By repeating this operation in sequence, the erase information data are stored in the erase information holding sections corresponding to the plural batch erase blocks to be erased. Successively, on the basis of the erase information data stored in the erase information holding sections, block erasing sections are activated to erase all the nonvolatile memory cells of each of the corresponding blocks where the erase information data are held.

Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Abstract: A semiconductor memory device including a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying a plurality of memory cells addressed by sequential addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number in response to cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles in response to the basic clock signal, and for instructing the counter circuit to count the number of cycles in

Abstract: In reading data, data is transferred to data registers starting from a data read start address to the last address at a row (page), and data at the next page is transferred to the data registers starting from a start address to the last address at that page. These operations are repeated. In writing data from an intermediate address of a page, predetermined data is written in data registers not having write data. It is possible to read data at consecutive pages from a first predetermined column address to the page last address, and to read data at consecutive pages from a second predetermined column address to the page last address. For the data structure having a first data structure and a second data structure, it is possible to continuously read a set of data having both the first and second data structures and a set of data having only the second data structure, improving the efficiency of a system using a semiconductor memory device.

Abstract: A semiconductor memory comprises a CMOS flip-flop circuit and a pair of N-channel MNOS (Metal Nitride Oxide Semiconductor) transistors. A first MNOS transistor is connected between a first pair of CMOS transistors and a second MNOS transistor is connected between a second pair of CMOS transistors. The gates of the first and second MNOS transistors are connected to a control signal line. The control signal line is normally maintained at a reference voltage. When an erase pulse of first polarity is supplied to the control signal line, the first and second MNOS transistors are turned ON, so that the memory operates in the static RAM mode. When a write pulse of second polarity is supplied to the control signal line, the data stored in the static RAM mode becomes nonvolatile.