Patents by Inventor Karanvir S. Grewal

Karanvir S. Grewal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190102539
    Abstract: Systems, apparatuses and methods may provide for technology that associates a key domain of a plurality of key domains with a customer boot image, receives the customer boot image from the customer, and verifies the integrity of the customer boot image that is to be securely installed at memory locations determined from an untrusted privileged entity (e.g., a virtual machine manager).
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: David M. Durham, Karanvir S. Grewal, Sergej Deutsch, Michael Lemay
  • Patent number: 10223528
    Abstract: Technologies for code flow integrity protection include a static analyzer that identifies a potential gadget in an atomic code path of a protected code. A marker instruction is inserted after the potential gadget with a parameter that corresponds to an address of the marker instruction, a hash evaluator instruction is inserted after an exit point of the atomic code path with a parameter that corresponds to the address of the marker instruction, and a compare evaluator instruction and a hash check instruction are inserted after the hash evaluator instruction. A target computing device executes the protected code and updates a path hash as a function of the parameter of the marker instruction, determines an expected hash value as a function of the parameter of the hash evaluator instruction, and generates an exception if the path hash and the expected hash value do not match. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Michael E. Kounavis, David M. Durham, Ravi L. Sahita, Karanvir S. Grewal
  • Publication number: 20190042369
    Abstract: In one embodiment, an apparatus comprises a controller comprising circuitry, the controller to generate an error correction code for a memory line, the memory line comprising a plurality of first data blocks, wherein the error correction code comprises parity bits generated based on first portions of a plurality of second data blocks, wherein the plurality of second data blocks are the first data blocks or diffused data blocks generated from the plurality of first data blocks; generate a metadata block corresponding to the memory line, wherein the metadata block comprises the error correction code for the memory line and at least one metadata bit; encode the first data blocks and the metadata block; and provide the encoded data blocks and the encoded metadata block for storage on a memory module.
    Type: Application
    Filed: September 17, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Sergej Deutsch, Wei Wu, David M. Durham, Karanvir S. Grewal
  • Publication number: 20190044954
    Abstract: Before sending a message to a destination device, a source device automatically uses a pattern matching algorithm to analyze entropy characteristics of a plaintext version of the message. The pattern matching algorithm uses at least one pattern matching test to generate at least one entropy metric for the message. The source device automatically determines whether the message has sufficiently low entropy, based on results of the pattern matching algorithm. In response to a determination that the message does not have sufficiently low entropy, the source device automatically generates integrity metadata for the message and sends the integrity metadata to the destination device. However, in response to a determination that the message has sufficiently low entropy, the source device sends the message to the destination device without sending any integrity metadata for the message to the destination device. Other embodiments are described and claimed.
    Type: Application
    Filed: December 5, 2017
    Publication date: February 7, 2019
    Inventors: Michael Kounavis, Amitabh Das, Sergej Deutsch, Karanvir S. Grewal, David M. Durham
  • Publication number: 20190036699
    Abstract: Technologies for end-to-end biometric-based authentication and locality assertion include a computing device with one or more biometric devices. The computing device may securely exchange a key between a driver and a secure enclave. The driver may receive biometric data from the biometric sensor in a virtualization-protected memory buffer and encrypt the biometric data with the shared key. The secure enclave may decrypt the biometric data and perform a biometric authentication operation. The computing device may measure a virtual machine monitor (VMM) to generate attestation information for the VMM. A secure enclave may execute a virtualization report instruction to request the attestation information. The processor may copy the attestation information into the secure enclave memory. The secure enclave may verify the attestation information with a remote attestation server. If verified, the secure enclave may provide a shared secret to the VMM. Other embodiments are described and claimed.
    Type: Application
    Filed: September 18, 2018
    Publication date: January 31, 2019
    Inventors: Ansuya Negi, Nitin V. Sarangdhar, Ulhas S. Warrier, Ramkumar Venkatachary, Ravi L. Sahita, Scott H. Robinson, Karanvir S. Grewal
  • Patent number: 10079684
    Abstract: Technologies for end-to-end biometric-based authentication and locality assertion include a computing device with one or more biometric devices. The computing device may securely exchange a key between a driver and a secure enclave. The driver may receive biometric data from the biometric sensor in a virtualization-protected memory buffer and encrypt the biometric data with the shared key. The secure enclave may decrypt the biometric data and perform a biometric authentication operation. The computing device may measure a virtual machine monitor (VMM) to generate attestation information for the VMM. A secure enclave may execute a virtualization report instruction to request the attestation information. The processor may copy the attestation information into the secure enclave memory. The secure enclave may verify the attestation information with a remote attestation server. If verified, the secure enclave may provide a shared secret to the VMM. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Ansuya Negi, Nitin V. Sarangdhar, Ulhas S. Warrier, Ramkumar Venkatachary, Ravi L. Sahita, Scott H. Robinson, Karanvir S. Grewal
  • Patent number: 10068068
    Abstract: A trusted time service is provided that can detect resets of a real-time clock and re-initialize the real-time clock with the correct time. The trusted time service provides a secure communication channel from an application requesting a timestamp to the real-time clock, so that malicious code (such as a compromised operating system) cannot intercept a timestamp as it is communicated from the real-time clock to the application. The trusted time service synchronizes wall-clock time with a trusted time server, as well as protects against replay attacks, where a valid data transmission (such as transmission of a valid timestamp) is maliciously or fraudulently repeated or delayed.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 4, 2018
    Assignee: Intel Corporation
    Inventors: Alpa T. Narendra Trivedi, Siddhartha Chhabra, Karanvir S. Grewal, David M. Durham
  • Patent number: 10061918
    Abstract: In one embodiment, a processor comprises: a first storage including a plurality of entries to store an address of a portion of a memory in which information has been modified; a second storage to store an identifier of a process for which information is to be stored into the first storage; and a first logic to identify a modification to a first portion of the memory and store a first address of the first portion of the memory in a first entry of the first storage, responsive to a determination that a current identifier of a current process corresponds to the identifier stored in the second storage. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 28, 2018
    Assignee: Intel Corporation
    Inventors: Salmin Sultana, David M. Durham, Michael Lemay, Karanvir S. Grewal, Ravi L. Sahita
  • Publication number: 20180189464
    Abstract: A trusted time service is provided that can detect resets of a real-time clock and re-initialize the real-time clock with the correct time. The trusted time service provides a secure communication channel from an application requesting a timestamp to the real-time clock, so that malicious code (such as a compromised operating system) cannot intercept a timestamp as it is communicated from the real-time clock to the application. The trusted time service synchronizes wall-clock time with a trusted time server, as well as protects against replay attacks, where a valid data transmission (such as transmission of a valid timestamp) is maliciously or fraudulently repeated or delayed.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Alpa T. Narendra Trivedi, Siddhartha Chhabra, Karanvir S. Grewal, David M. Durham
  • Publication number: 20180095812
    Abstract: Methods, apparatus, and system to analyze a memory integrity violation and determine whether its cause was hardware or software based.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: SERGEJ DEUTSCH, KARANVIR S. GREWAL, MICHAEL E. KOUNAVIS
  • Publication number: 20180089422
    Abstract: Technologies for code flow integrity protection include a static analyzer that identifies a potential gadget in an atomic code path of a protected code. A marker instruction is inserted after the potential gadget with a parameter that corresponds to an address of the marker instruction, a hash evaluator instruction is inserted after an exit point of the atomic code path with a parameter that corresponds to the address of the marker instruction, and a compare evaluator instruction and a hash check instruction are inserted after the hash evaluator instruction. A target computing device executes the protected code and updates a path hash as a function of the parameter of the marker instruction, determines an expected hash value as a function of the parameter of the hash evaluator instruction, and generates an exception if the path hash and the expected hash value do not match. Other embodiments are described and claimed.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventors: Michael E. Kounavis, David M. Durham, Ravi L. Sahita, Karanvir S. Grewal
  • Publication number: 20180091308
    Abstract: In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.
    Type: Application
    Filed: November 17, 2017
    Publication date: March 29, 2018
    Inventors: David M. Durham, Rajat Agarwal, Siddhartha Chhabra, Sergej Deutsch, Karanvir S. Grewal, Ioannis T. Schoinas
  • Publication number: 20180074975
    Abstract: Embodiments of apparatus, method, and storage medium associated with multi-stage memory integrity for securing/protecting memory content are described herein. In some embodiments, an apparatus may include multiple stages having respective encryption engines to encrypt data in response to a write or restore operation; wherein the encryption engines are to successively encrypt the data in a plurality of encryption stages using a plurality of tweaks based on a plurality of selectors of different types {s1, s2, . . . }. In embodiments, the multiple stages may further comprise one or more decryption engines to partially, fully, or pseudo decrypt the plural encrypted data, in response to a read, move or copy operation; wherein the one or more decryption engines are to partially, fully, or pseudo decrypt the plural encrypted data in one or more decryption stages using one or more tweaks based on a subset of the selectors of different types {s1, s2, . . . }.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: SERGEJ DEUTSCH, DAVID M. DURHAM, KARANVIR S. GREWAL, MICHAEL E. KOUNAVIS
  • Patent number: 9893897
    Abstract: Technologies are provided in example embodiments for analyzing an encrypted network flow. The technologies include monitoring the encrypted network flow between a first node and a second node, the network flow initiated from the first node; duplicating the encrypted network flow to form a copy of the encrypted network flow; decrypting the copy of the encrypted network flow using a shared secret, the shared secret associated with the first node and the second node; and scanning the network flow copy for targeted data.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Xiaoning Li, Karanvir S. Grewal, Geoffrey H. Cooper, John R. Guzik
  • Publication number: 20180018288
    Abstract: In one embodiment, an apparatus includes: at least one core to execute instructions, the at least one core formed on a semiconductor die; a first memory formed on the semiconductor die, the first memory comprising a non-volatile random access memory, the first memory to store a first entry to be a monotonic counter, the first entry including a value field and a status field; and a control circuit, wherein the control circuit is to enable access to the first entry if the apparatus is in a secure mode and otherwise prevent the access to the first entry. Other embodiments are described and claimed.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Prashant Dewan, Siddhartha Chhabra, David M. Durham, Karanvir S. Grewal, Alpa T. Narendra Trivedi
  • Patent number: 9832015
    Abstract: Both end-to-end security and traffic visibility may be achieved by a system using a controller that derives a cryptographic key that is different for each client based on a derivation key and a client identifier that is conveyed in each data packet. The controller distributes the derivation key to information technology monitoring devices and a server to provide traffic visibility. For large key sizes, the key may be derived using a derivation formula as follows: client_key_MSB=AES128(base_key_1, client_ID),??(1) client_key_LSB=AES128(base_key_2, client_ID+pad), and??(2) client_key=client_key_MSB?client_key_LSB, where (1) and (2) are executed in parallel. The client key and a client identifier may be used so that end-to-end security may be achieved.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Men Long, Jesse Walker, Karanvir S Grewal
  • Publication number: 20170286672
    Abstract: In one embodiment, a processor comprises: a first storage including a plurality of entries to store an address of a portion of a memory in which information has been modified; a second storage to store an identifier of a process for which information is to be stored into the first storage; and a first logic to identify a modification to a first portion of the memory and store a first address of the first portion of the memory in a first entry of the first storage, responsive to a determination that a current identifier of a current process corresponds to the identifier stored in the second storage. Other embodiments are described and claimed.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Salmin Sultana, David M. Durham, Michael Lemay, Karanvir S. Grewal, Ravi L. Sahita
  • Publication number: 20170285976
    Abstract: Apparatus, systems, computer readable storage mediums and/or methods may provide memory integrity by using unused physical address bits (or other metadata passed through cache) to manipulate cryptographic memory integrity values, allowing software memory allocation routines to control the assignment of pointers (e.g., implement one or more access control policies). Unused address bits (e.g., because of insufficient external memory) passed through cache, may encode key domain information in the address so that different key domain addresses alias to the same physical memory location. Accordingly, by mixing virtual memory mappings and cache line granularity aliasing, any page in memory may contain a different set of aliases at the cache line level and be non-deterministic to an adversary.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: David M. Durham, Siddhartha Chhabra, Michael E. Kounavis, Sergej Deutsch, Karanvir S. Grewal, Joseph F. Cihula, Saeedeh Komijani
  • Patent number: 9769123
    Abstract: One particular example implementation of an apparatus for mitigating unauthorized access to data traffic, comprises: an operating system stack to allocate unprotected kernel transfer buffers; a hypervisor to allocate protected memory data buffers, where data is to be stored in the protected memory data buffers before being copied to the unprotected kernel transfer buffers; and an encoder module to encrypt the data stored in the protected memory data buffers, where the unprotected kernel transfer buffers receive a copy the encrypted data.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Karanvir S. Grewal, Ravi L. Sahita, David Durham
  • Publication number: 20170185776
    Abstract: Systems, apparatuses and methods may provide for verifying, from outside a trusted computing base of a computing system, an identity an enclave instance prior to the enclave instance being launched in the trusted computing base, determining a memory location of the enclave instance and confirming that the memory location is local to the computing system. In one example, the enclave instance is a proxy enclave instance, wherein communications are conducted with one or more additional enclave instances in the trusted computing base via the proxy enclave instance and an unencrypted channel.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Inventors: Scott H. Robinson, Ravi L. Sahita, Mark W. Shanahan, Karanvir S. Grewal, Nitin V. Sarangdhar, Carlos V. Rozas, Bo Zhang, Shanwei Cen